Shaoqiang Zhang

A 130nm RFSOI technology with switch, LNA, and EDNMOS devices for integrated front-end module SoC applications

The cellular frequency spectrum has become increasingly complex with over 50 frequencies in LTE standards. To reduce costs in the front end module the switch has migrated from a III-V PHEMT base to a silicon solution in RFSOI. While many providers have focused on a 180nm base technology node for the RFSOI there has been an increasing move to more advanced nodes to solution the logic requirements of the cellular standards. In addition there has been a strong interest in migrating to an SOC solution in RFSOI. In this paper a 130nm RFSOI technology is presented with high performance and low noise body tied 1.5V NMOS for LNA devices with a novel method of body contacting, low Ron*Coff NMOS for antenna switch and state of the art EDNMOS with fT of 38GHz and BVdss of 14V BVdss for integrated PA application. Specific results presented include characterization of the switch, LNA, and Power Amplifier devices.

A DC-50 GHz SPDT switch with maximum insertion loss of 1.9 dB in a commercial 0.13-μm SOI technology

In this paper, a low insertion loss, high isolation, ultra wideband (DC to 50 GHz) single-pole double-throw (SPDT) switch using 0.13 μm SOI technology is presented. The switch is designed by using a series-shunt configuration with input and output matching networks. The channel length and gate bias impacts on switch performance are studied. It is found that the transistor channel length has dominant effects on both the insertion loss and isolation. The measured insertion loss of the SPDT with 0.13 μm channel length transistor is less than 1.9 dB up to 50 GHz, while the isolation is better than 27 dB. Measured P1dB for SPDT switch is larger than 12 dBm. The active chip area of designed SPDT switch is only 0.21 × 0.19 mm2.

A Novel device for low noise amplification in 130nm high resistivity RFSOI technology platform

CMOS Silicon on Insulator (SOI) is now the technology of choice for RF switches in front end module systems. The emergence of 4G cellular systems with carrier aggregation has made the design of front end modules more complex. To take into account the diversity paths now required in cellular systems the low noise amplifiers (LNAss) are being integrated in the front end module along with the switches. This paper describes novel low noise amplifier devices in high resistivity SOI targeted for integration and use in RF front end modules.

An optimized isolated 5V EDMOS in 55nm LPx platform for use in Power Amplifier applications

Power Amplifier (PA) modules are becoming more and more complex in modern wireless systems. In order to meet the efficiency/linearity design schemes such as Envelope elimination and restoration (EER) and Envelope tracking (ET) are increasingly becoming popular in PA applications. This paper describes an optimized isolated 5V EDMOS in 55nm Low Power extended (LPx) platform which is ideal for use in the bias modulator and controller of the PA module. Industry leading Rsp of 0.96 mohm-mm2 for high voltage NMOS and 2.6 mohm-mm2 for the high voltage PMOS is reported. Drain to source breakdown voltages of 10.5V was achieved for these devices. Due to special considerations given to optimizing the CGD capacitance while maintaining the Rsp, high Johnsons figure of merit (fT*BVDS) of 536 GHz-V and 168 GHz-V were achieved for the NMOS and PMOS respectively.