Sharbel E. Noujaim

System and method employing pipelined parallel circuit architecture for displaying surface structures of the interior region of a solid body

Arbitrary interior surfaces of a three-dimensional body are displayed from a regular array of values of at least one physical property in the interior of the body. The physical property measurements may be made with systems such as computerized tomographic x-ray, or magnetic resonance imaging. Highly parallel circuits and a highly parallel architecture permit generation of surface views in real time, i.e., sufficiently fast to support ongoing procedures such as surgical operations. These parallel circuits, realizable on large scale integrated circuit chips, perform surface normal calculations, linear interpolations and signal comparisons in simultaneously operating circuit paths which are asynchronously enabled when input data appear.

30MHz compiled chip set for graphics computations

A 1.25μm CMOS chip that has attained a device density of 1500 transistors/mm2, using a silicon compiler for design, will be described. The bit-slice elements of the chip communicate serially to implement a pipeline with a throughput of 50 million multiply/accumulates/s at a 30MHz clock rate.

Architecture for ultrasonic imaging

An ultrasonic imaging processing system includes transducers and means to generate in an analog fashion, in-phase and quadrature phase signals. These signals are converted to digital form and a butterfly phase rotator circuit is employed to correct for phase differences in beam steering and focusing. In particular, speed and simplicity is achieved through the utilization of read only memory means providing appropriate function values for phase correction in conjunction with digital multiplication and summing circuitry.

Multichannel data acquisition system with on-chip digital signal processing

A single-chip 30-channel data acquisition system for power management applications has been successfully designed, fabricated, and tested. This mixed analog/digital single-chip system is composed of three delta-sigma A/D (analog-to-digital converters which have 11 bits of resolution each and an oversample clock of 3.58 MHz. The dedicated digital signal processor has a 32-bit twos-complement, fixed-point architecture and performs low-pass filtering, accumulation, and data selection and comparison.<<ETX>>