Sharma Pamarthy

High aspect ratio silicon etch: A review

High aspect ratio (HAR) silicon etch is reviewed, including commonly used terms, history, main applications, different technological methods, critical challenges, and main theories of the technologies. Chronologically, HAR silicon etch has been conducted using wet etch in solution, reactive ion etch (RIE) in low density plasma, single-step etch at cryogenic conditions in inductively coupled plasma (ICP) combined with RIE, time-multiplexed deep silicon etch in ICP-RIE configuration reactor, and single-step etch in high density plasma at room or near room temperature. Key specifications are HAR, high etch rate, good trench sidewall profile with smooth surface, low aspect ratio dependent etch, and low etch loading effects. Till now, time-multiplexed etch process is a popular industrial practice but the intrinsic scalloped profile of a time-multiplexed etch process, resulting from alternating between passivation and etch, poses a challenge. Previously, HAR silicon etch was an application associated primarily ...

Process Integration Considerations for 300 mm TSV Manufacturing

Through-silicon via (TSV) will transition to high volume production when end-customer value (as exhibited by functionality, performance, form factor, etc.) are delivered at equivalent yield and cost. While this has been successfully achieved for CMOS image sensors (starting with 200 mm), significant work remains to be done in the TSV value chain (design-materials-process-packaging-test) in the communication and memory segments. This paper will address key unit process/process-integration challenges and highlight recent internal/ partner and industry findings in the context of TSV manufacturability at 300 mm.