Shen-De Wang

Negative Bias Temperature Instability in Low-Temperature Polycrystalline Silicon Thin-Film Transistors

The authors have proved that negative bias temperature instability (NBTI) is an important reliability issue in low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs). The measurements revealed that the threshold-voltage shift is highly correlated to the generation of grain-boundary trap states. Both these two physical quantities follow almost the same power law dependence on the stress time; that is, the same exponential dependence on the stress voltage and the reciprocal of the ambient temperature. In addition, the threshold-voltage shift is closely associated with the subthreshold-swing degradation, which originates from dangling bond formation. By expanding the model proposed for bulk-Si MOSFETs, a new model to explain the NBTI-degradation mechanism for LTPS TFTs is introduced

CF4 Plasma Treatment for Fabricating High-Performance and Reliable Solid-Phase-Crystallized Poly-Si TFTs

A CF 4 plasma treatment on solid-phase-crystallized (SPC) poly-Si thin-film transistors (TFTs) has been demonstrated. Using this technique, fluorine atoms can be introduced into the poly-Si film to passivate the defects, and hence, the device performance of the SPC poly-Si TFTs can be significantly improved. The fluorinated SPC poly-Si TFTs exhibit a good subthreshold slope, low threshold voltage, and high field effect mobility. Moreover, the fluorinated SPC poly-Si TFTs also exhibit an improved hot-carrier-stress immunity, which is due to the strong Si-F bonds formed in the poly-Si channel region.

Bias Temperature Instabilities for Low-Temperature Polycrystalline Silicon Complementary Thin-Film Transistors

cToppoly Optoelectronics Corporation, Chu-Nan 350, Miaoli County, Taiwan The degradation mechanisms of both negative bias temperature instability NBTI and positive bias temperature instability PBTI were studied for low-temperature polycrystalline silicon complementary thin-film transistors. Measurements show that both NBTI and PBTI are highly bias dependent; however, the effect of the temperature is only functional on the NBTI stress. Furthermore, instead of interfacial trap-state generation during the NBTI stress, the PBTI stress passivates the interface trap states. We conclude that the diffusion-controlled electrochemical reactions dominate the NBTI degradation while charge trapping in the gate dielectric

A Reliability Model for Low-Temperature Polycrystalline Silicon Thin-Film Transistors

We proposed here a reliability model that successfully introduces both the physical mechanisms of negative bias temperature instability (NBTI) and hot carrier stress (HCS) for p-channel low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs). The proposed model is highly matched with the experimental results, in which the NBTI dominates the device reliability at small negative drain bias while the HCS dominates the degradation at large negative drain bias. In summary, the proposed model provides a comprehensive way to predict the lifetime of the p-channel LTPS TFTs, which is especially necessary for the system-on-panel circuitry design

Analysis of Negative Bias Temperature Instability in Body-Tied Low-Temperature Polycrystalline Silicon Thin-Film Transistors

Negative bias temperature instability (NBTI) degradation mechanism in body-tied low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) is analyzed by the charge-pumping (CP) technique. The properties of bulk trap states (including interface and grain boundary trap states) are directly characterized from the CP current. The increase of the fixed oxide charges is also extracted, which has not been quantified in previous studies of NBTI degradation in LTPS TFTs. The experimental results confirm that the NBTI degradation in LTPS TFTs is caused by the generation of bulk trap states and oxide trap states.

A novel process-compatible fluorination technique with electrical characteristic improvements of poly-Si TFTs

A process-compatible fluorine passivation technique of poly-Si thin-film transistors (TFTs) was demonstrated by employing a novel CF/sub 4/ plasma treatment. Introducing fluorine atoms into poly-Si films can effectively passivate the trap states near the SiO/sub 2//poly-Si interface. With fluorine incorporation, the electrical characteristics of poly-Si TFTs can be significantly improved including a steeper subthreshold slope, smaller threshold voltage, lower leakage current, higher field-effect mobility, and better on/off current ratio. Furthermore, the CF/sub 4/ plasma treatment also improves the reliability of poly-Si TFTs with respect to hot-carrier stress, which is due to the formation of strong Si-F bonds.

Electrical characteristics and reliability of multi-channel polycrystalline silicon thin-film transistors

We demonstrate the fabrication process and the electrical characteristics of n-channel polycrystalline silicon thin-film transistors (poly-Si TFTs) with different numbers of channel stripes. The devices electrical characteristics, such as on-current, threshold voltage, and subthreshold swing, were improved by increasing the number of channel stripes due to the enhancement of gate control. However, the electric field strength near the drain side was enlarged in multi-channel structures, causing severe impact ionization. The degradation of devices reliability under various electrical stress conditions was suggested.

Plasma Damage-Enhanced Negative Bias Temperature Instability in Low-Temperature Polycrystalline Silicon Thin-Film Transistors

In this letter, a mechanism that will make negative bias temperature instability (NBTI) be accelerated by plasma damage in low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) is presented. The experimental results confirm that the mechanism, traditionally found in the thin gate-oxide devices, does exist also in LTPS TFTs. That is, when performing the NBTI measurement, the LTPS TFTs with a larger antenna ratio will have a higher degree in degradation of the threshold voltage, effective mobility, and drive current under NBTI stress. By extracting the related device parameters, it was demonstrated that the enhancement is mainly attributed to the plasma-damage-modulated creating of interfacial states, grain boundary trap states, and fixed oxide charges. It could be concluded that plasma damage will speed up the NBTI and should be avoided for the LTPS TFT circuitry design

Plasma-induced damage on the performance and reliability of low-temperature polycrystalline silicon thin-film transistors

We have investigated the impact of plasma-induced damage on the performance and reliability of low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs). The LTPS TFTs having different antenna structures were used to study the effects of the plasma-etching process. We observed that performance instability occurred for the devices having a relatively large-area antenna. Plasma damage mainly caused nonuniform distribution of the threshold voltages in the LTPS TFTs, presumably because of charge trapping in the gate dielectric during the plasma-etching process. The reliabilities of the LTPS TFTs having larger antenna areas were found to be more degraded under gate-bias stress and hot-carrier stress than those of the samples having smaller antenna areas. Because of their enhanced plasma damage, we speculate that the LTPS TFTs having larger antenna areas possess more trap states in the gate dielectrics. During gate-bias stress or hot-carrier stress, therefore, charges can be injected into the gate dielectric through trap-assisted tunneling, resulting in significant degradation of both the performance and reliability.