T. F. Lei

A physical model for the hysteresis phenomenon of the ultrathin ZrO2 film

This work studies and presents an inner-interface trapping physical model for the ultra-thin (effective oxide thickness=15 A) zirconium oxide (ZrO2) film to explain its hysteresis phenomenon. The shift of the capacitance–voltage characteristics swept from accumulation to inversion and then swept back with light illumination is about 110 mV, which is larger than the shift without light illumination (∼45 mV). The mobile ion effect is obviated using bias-temperature stress measurement. The proposed model successfully explains not only the phenomenon but also the thickness effect for the capacitance–voltage characteristics and the different turn-around voltages of the current density–voltage characteristics of the zirconium dielectrics.

Mechanism of nitrogen coimplant for suppressing boron penetration in p+‐polycrystalline silicon gate of p metal–oxide semiconductor field effect transistor

The mechanism of the nitrogen co‐implant to suppress the boron penetration in p+‐polycrystalline silicon gate has been investigated. The nitrogen coimplant with the BF+2 combines with the boron to form a B–N complex which results in a retardation of boron diffusion. It is found that metal–oxide–silicon capacitors with nitrogen implantation show improved electrical properties.

Impact of High-

In this letter, 65-nm node silicon-on-insulator devices with high-kappa offset spacer dielectric were investigated by extensive 2-D device simulation. The result shows that the high-kappa offset spacer dielectric can effectively increase the on-state driving current ION and reduce the off leakage current IOFF due to the high vertical fringing electric field effect. This fringing field can significantly improve the ION/IOFF current ratio and the subthreshold swing compared with the conventional oxide spacer. Consequently, the gate-to-channel control ability is enhanced by the fringing field via the high-kappa offset spacer dielectric

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The influences of cladding layer thicknesses on the performance of strained‐layer InGaAs/GaAs graded‐index separated confinement heterostructure quantum well lasers have been studied. The waveguiding property of the laser structure was analyzed using the transfer matrix method. In this work, experimental results and the calculated results showed that threshold current densities and external quantum efficiencies both were crucially dependent on the thicknesses of cladding layer for both single and multiple quantum well lasers. The minimum cladding layer thicknesses needed to maintain low threshold current densities and low internal total loss for both single and multiple quantum well devices were determined experimentally and theoretically.

Offset Spacer in 65-nm Node SOI Devices

The electrical characteristics of ultra-shallow p/sup +//n junctions formed by implanting a 60 keV Ge/sup +/ into a TiSi/sub 2/ layer have been studied. A very low reverse leakage current density (/spl cong/0.4 nA/cm/sup 2/ at -5 V) and a very good forward ideality factor n (/spl cong/1.001) were achieved in these ultra-shallow p/sup +//n junctions. From the secondary ion mass spectrometry (SIMS) analysis, the junction depth was measured to be 600 /spl Aring/ and the surface concentration was about 3 times higher than that of the conventional samples.

Role of cladding layer thicknesses on strained-layer InGaAs/GaAs single and multiple quantum well lasers

A high-performance polysilicon contacted shallow junction diode formed by using a stacked-amorphous-silicon (SAS) film as the diffusion source is reported. The diode exhibited a very low leakage current (<or=1 nA/cm/sup 2/ at -5 V), a very high breakdown voltage (>or=100 V), and a forward ideality factor m<or=1.05 over seven decades.<<ETX>>

The influence of Ge-implantation on the electrical characteristics of the ultra-shallow junction formed by using silicide as a diffusion source

A process-compatible fluorine passivation technique of poly-Si thin-film transistors (TFTs) was demonstrated by employing a novel CF/sub 4/ plasma treatment. Introducing fluorine atoms into poly-Si films can effectively passivate the trap states near the SiO/sub 2//poly-Si interface. With fluorine incorporation, the electrical characteristics of poly-Si TFTs can be significantly improved including a steeper subthreshold slope, smaller threshold voltage, lower leakage current, higher field-effect mobility, and better on/off current ratio. Furthermore, the CF/sub 4/ plasma treatment also improves the reliability of poly-Si TFTs with respect to hot-carrier stress, which is due to the formation of strong Si-F bonds.

High-performance polysilicon contacted shallow junctions formed by stacked-amorphous-silicon films

In this study, we report a high‐performance ultrathin oxide (≊80 A) prepared by a low‐temperature wafer loading and N2 preannealing before oxidation. This recipe can reduce native oxide thickness and thermal stress compared to the conventional oxidation recipe. The high‐resolution transmission electron microscopy reveals that the SiO2/Si interface is atomically flat, and a thin crystalline‐like oxide layer about 7 A exists at the interface. Oxides prepared by the proposed recipe show a very high dielectric breakdown field (≥16 MV/cm) and a very low interface state density (Nit ≊ 3 × 109 eV−1u2009cm−2 at midgap). The effective barrier height at cathode derived from the slopes of log(Jg/E2ox) vs 1/Eox and tbd vs 1/Eox plots is about 3.9 eV, instead of 3.2 eV for the control sample. It also shows a better immunity to the charge trapping and interface state generation under high‐field stressing, and superior time‐dependent dielectric breakdown characteristics.

A novel process-compatible fluorination technique with electrical characteristic improvements of poly-Si TFTs

In this letter, polycrystalline-silicon thin-film transistors (poly-Si TFTs) with 50-nm nanowire (NW) channels, which are fabricated without advanced photolithography by using a sidewall spacer-formation technique, are proposed for the first time. Because the polygate electrode is perpendicularly across poly-Si NW channels to form a trigatelike structure, the proposed poly-Si NW TFT owns outstanding gate controllability. In summary, a simple and low-cost scheme is proposed to fabricate high-performance poly-Si NW TFT suitable for future display manufacturing and practical applications.

Characterization of ultrathin oxide prepared by low‐temperature wafer loading and nitrogen preannealing before oxidation

The charge loss mechanism in a hafnium oxide (HfO2 ) dielectric dot flash memory is investigated. We measure the temperature and time dependence of a charge loss induced gate leakage current in a large area cell directly. We find that (1) the charge loss is through a top oxide in the cell and (2) the stored charge emission process exhibits an Arrhenius relationship with temperature, as opposed to linear temperature dependence in a semiconductor-oxide-nitride-oxide-semiconductor flash memory. A thermally activated tunneling front model is proposed to account for the charge loss behavior in a HfO2 dot flash memory.