Jam Wem Lee

Highly Reliable Nickel Silicide Formation with a Zr Capping Layer

Department of Electronics Engineering, National Chiao-Tung University, Hsin-Chu, TaiwanZr is proposed to be the capping layer for nickel silicide to obtain a stable low resistance contact system even at an annealingtemperature as high as 850°C. A NiSi monolayer is the only phase observed in those samples annealed from 500 to 850°C.Experimental results from transmission electron microscopy and X-ray diffractometry analysis show that the agglomeration andprecipitate of nickel silicide problems which are usually encountered in the NiSi system are eliminated.© 2003 The Electrochemical Society. @DOI: 10.1149/1.1563093# All rights reserved.Manuscript submitted November 11, 2002; revised manuscript received January 8, 2003. Available electronically March 7, 2003.

High reliability polyoxide fabricated by using TEOS oxide deposited on disilane polysilicon film

This paper reports the TEOS oxide deposited on the polysilicon film which was prepared by using the disilane chemical vapor deposition. Compared to the thermally grown oxide or TEOS (tetra-ethyl-ortho-silicate) oxide deposited on the conventional silane polysilicon film, it had symmetrical J-E characteristics that had lower leakage currents but much higher breakdown field, a lower electron trapping rate, and a much larger charge to breakdown. These good properties are attributed to the smoother surface of the deposited disilane poly-I film and the more incorporation of nitrogen during the rapid thermal annealing (RTA) in N/sub 2/O ambient. It is suitable to be as the inter-polyoxide of the electrically-erasable programmable read only memory (EEPROM).

Electrostatic discharge protection under pad design for copper-low-K VLSI circuits

An electrostatic discharge (ESD) under pad structure is proposed and demonstrated for the novel copper-low-K circuit design. By using this approach, the density of both devices and pads could be markedly improved; in a rough estimation, approximately five to twenty percent of the chip area could be saved. Moreover, tests of ESD, latch-up, and bond yield are performed and are found to be better than those of the conventional ones. The designed structure could be considered as a very effective achievement, and this is particularly true for the sub-0.1 µm circuit with copper-low-K interconnections.

Growing High-Performance Tunneling Oxide by CF 4 Plasma Pretreatment

Thin tunneling oxides grown on a CF 4 pretreated silicon substrate were prepared and investigated for the first time. The tunneling current of the CF 4 -treated oxide is about three orders of magnitude higher than that of thermal oxide; furthermore, the stress-induced anomalous current and low electric field leakage current were greatly suppressed. The improvement was attributed to the incorporation of fluorine in the oxide region. Both control and CF 4 -treated devices exhihited comparable channel mobility. However, pretreatment with CF 4 markedly improved the reliability of the insulator. This oxide is highly promising for fabricating low-voltage electrically erasable and programmable read-only memories (EEPROMs) without increasing the complexity of the process.

The enhancement of nitrogen incorporation in RTN2O annealed TEOS oxide fabricated on disilane-based polysilicon films

Disilane-based stacked structures were first proposed to demonstrate that the nitrogen incorporation was enhanced in the RTN 2 O annealed tetraethylorthosilicate (TEOS) oxide fabricated on disilane-based polysilicon films, Compared with the oxide fabricated on the silane-based polysilicon film, the nitrogen incorporation in the disilane-based oxides is six times higher. To study the nitrogen incorporation effects on the RTN 2 O annealed TEOS oxides, the disilane-based polysilicon stacked on the silane-based polysilicon film structure was proposed. We found that the oxide quality was largely improved by the same surface morphology of bottom polysilicon films. We think the this approach could he used in fabricating dynamic random access memory (DRAM) to have better data retention characteristics and to improve the reliability of DRAM and flash memory devices.

Characterization of Novel HfTiO Gate Dielectrics Post-treated by NH3 Plasma and Ultra-violet Rays

by NH3 Plasma and Ultra-violet Rays Jer Chyi Wang, Woei Cherng Wu, Chao Sung Lai, Jam Wem Lee, Kuo Cheng Chiang, De Ching Shie, Tan Fu Lei, and Chung Len Lee Nanya Technology Corporation, Kueishan 333, Taoyuan, Taiwan Department of Electronic Physics, National Chiao Tung University, Hsinchu 300, Taiwan Department of Electronics Engineering, Chang Gung University, Kweishan 333, Taoyuan, Taiwan National Nano Device Laboratories, Hsinchu 300, Taiwan Department of Electronics Engineering, National Chiao Tung University, Hsinchu 300, Taiwan Phone:+886-3-2118800 Ext.5786 Fax:+886-3-2118507 email:cslai@mail.cgu.edu.tw

High reliability ultrathin interpolyoxynitride dielectrics prepared by N2O plasma annealing

This work addresses the preparation of ultrathin (effective oxide thickness, 42 A) interpoly-oxynitride (SiO x N y ) films by annealing thin nitride films with high density N 2 O plasma and N 2 O rapid thermal annealing. The proposed oxynitride dielectrics formed using N 2 O plasma annealing exhibited low gate leakage current, high breakdown electric field, long ten-year lifetime, and large effective barrier height. These superior properties can be attributed to the high concentration of oxygen incorporated in the poly-II/nitride interface and a reduction of the trap density of the interpoly-oxynitride films. The dielectric is a suitable substitute for the inter-polyoxide of electrically-erasable programmable read only memory.

Thin oxides grown on disilane-based polysilicon

This report describes the thin oxide (<10 nm) thermally grown on polysilicon film, which was prepared by disilane (Si2H6) chemical vapor deposition. In comparison with the thin oxide grown on conventional silane (SiH4) polysilicon film, the prepared oxides have lower leakage currents, a lower electron trapping rate and a larger charge to breakdown distribution. These good properties are attributed to the smooth surface of the disilane poly-I film. This film is suitable for use as the interpoly oxide of electrically-erasable programmable read only memory.

Improvements in Both Thermal Stability of Ni-Silicide and Electrical Reliability of Gate Oxides Using a Stacked Polysilicon Gate Structure

A process design is presented for improving the thermal stability of Ni-silicide (nickel-silicide) using a stacked polysilicon gate structure, The Ni-silicide formed has low sheet resistance up to 800°C on a silicidation process. Additionally, the metal-oxide-semiconductor (MOS) capacitors fabricated using these proposed gate structures demonstrate higher electrical reliability for gate oxides than those of nonstacked films. That is, the gate oxides of the MOS capacitors were only slightly degraded after silicidation step at 800°C. In conclusion, the Ni-silicide formed on those stacked polysilicon gates are attractive in fabricating ultralarge scale integration (ULSI) circuits because both the thermal stability of Ni-silicide and the reliability of gate oxides are improved simultaneously.

Thin tunnel oxide grown on silicon substrate pretreated by CF 4 plasma

High tunneling current and large resistance against stress were the main issue of tunnel oxide for scaling down the operation voltage of EEPROMs. In this letter, thin-tunnel oxides grown on a CF/sub 4/ pretreated silicon substrate were prepared and investigated for the first time. The fabricated oxide has about three orders of tunneling current higher than that of control one; furthermore, the stress induced anomalous and low electric field leakage currents were greatly suppressed. The improvement could be contributed to F-incorporation in oxide. This type of oxide is suitable for fabricating low-voltage EEPROMs and less process complexity was added.