Shiang-Shi Kang

Short-Channel Characteristics of Self-Aligned

A novel device architecture-the self-aligned pi-shaped source/drain (S/D) ultrathin silicon-on-insulator (UTSOI) FET-is presented for the first time in the field of silicon-on-insulator (SOI) technology; this new device demonstrates how to decrease the self-heating effects in the SOI-based devices. Two-dimensional simulations show that the cost of building an S/D tie into the UTSOI-FET is a modest degradation of the short-channel characteristics including drain-induced barrier lowering (DIBL) and subthreshold swing (SS), when compared with a traditional UTSOI-FET. This degradation occurs because the S/D-tied scheme introduces two additional pathways between the S/D regions and the silicon substrate, thereby reducing the gates ability to control the channel. Yet, the results presented here show these negative effects to be reasonably small (e.g., DIBL ang 90 mV/V and SS ang 100 mV/dec), whereas the positive effect of reduced self-induced heating is substantial and significantly improves device reliability.

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This paper aims to comprehensively examine the electrical characteristics of a new silicon-on-insulator (SOI) device structure with source/drain (S/D) tie as a function of the block oxide height. According to the 2-D simulations, the height of the block oxide enclosing the silicon body is one of the key parameters for determining the device properties and their fluctuations. Additionally, the self-heating effects (SHEs) can be well controlled chiefly due to the presence of the S/D-tied scheme.

-Shaped Source/Drain Ultrathin SOI MOSFETs

This paper proposes a new self-aligned process to form the silicon-on-insulator with block oxide. Based on the TCAD simulation, we have proved that the new process can get excellent short-channel effects immunity compared to the previous process [1]. Also, the new process can overcome the problem of the previous one, which can not be used on the thin BOX devices, so that the application of the block oxide can be applied extensively. In addition, we study how the height of the block oxide affects the devices performance in detail. Finally, we demonstrate a novel floating body cell using block oxide for 1T-DRAM application and its memory characteristics, large programming window and low leakage, are better than the conventional counterpart.

Misalignment of the Block Oxide Height in Self-aligned Source/Drain-tied bFDSOI-FET

A self-aligned novel S/D tie SOI device is presented for the first time in the field of silicon on insulator technology. The new device having thick-body and body-passway is demonstrated to improve the self-heating effect and decrease the parasitic source/drain resistance. When the source/drain-tie length is too small or too big, the negative differential conductance behavior can be observed. It can be achieved that the lattice temperature of the new device is reduced 32% when compared with the two conventional SOI devices.

A new process for self-aligned silicon-on-insulator with block oxide and its memory application for 1T-DRAM

This work aims to examine and analyze carefully the effects of block oxide length (LBO) in a 40 nm multi-substrate-contact field-effect transistor (MSCFET). In addition, the proposed structure is based on the self-aligned (SA) gate-to-body technique. In the MSCFET design the two key parameters are the length and the height of the block oxide which are so sensitive to the short-channel effects (SCEs). Because the research of the block oxide height (HBO) has already been done as described in [1], in this study we will focus on the influence of LBO on the SA-MSCFET. Also, some preliminary characteristics of the new configuration developed are demonstrated by using TCAD simulations.

The influence of the source/drain-tie length in a novel self-aligned S/D tie SOI for improving self-heating

In this paper, for the first time, a novel devise-architecture namely multi-source/drain SOI MOSFET is proposed and compared with a conventional SOI MOSFET. According to the simulation result, our proposed transistor not only maintains the desirable short channel behaviour, but also enhances the on/off current ratio due to the multi-source/drain scheme.

A study of L BO effects in a 40 nm SA-MSCFET

What is silicon-on-insulator (SOI)? Why SOI? Because of the excellent short-channel effects (SCEs) immunity, SOI group is generally considered to be a very strong candidate in the end of the CMOS (complementary metal-oxide semiconductor) scaling, as compared to bulk silicon. This paper aims to propose a novel device architecture namely self-aligned (SA) Pi-shaped source/drain ultra-thin SOI MOS field-effect transistor (Pi-S/D UTSOI MOSFET). Although this approach is based on simulation, numerical simulations, it demonstrates the trends of electrical characteristics in the proposed structure. This work also illustrates the process simulation and the tradeoff between the self-heating and the short-channel behaviors which are two important attributes of the future scaled-down UTSOI devices.

Simulation of the multi-source/drain SOI MOSFET

A non-classical device structure namely self-aligned quasi-silicon-on-insulator (SOI) metal-oxide semiconductor (MOS) field-effect transistor with pi-shaped semiconductor conductive layer (SA-piFET) is presented, seeking to improve the performance and upgrade the reliability of the SOI-based devices. Designed to equip with a SA single crystal silicon channel layer, plus a natural source/drain (S/D) tie and a block oxide island (BOI) under the channel, the SA-piFET, by minimizing the self-heating and charge sharing issues, thus manages to obtain better stability and reliability. Based on two-dimensional (2-D) simulations, the S/D tie serves to reduce the lattice-atom thermal vibrations and the BOI under the channel is used to control the short-channel effects (SCEs). Also, although the electrical characteristics of the SA-piFET are somewhat worse than the SA recessed S/D (ReS/D) ultra-thin (UT) SOI, it works without self-heating increasing.

Self-aligned n-shaped source/drain ultra-thin SOI MOSFETs

In this work, our main aim is to investigate the effects of source/drain thickness on the characteristics of self-aligned quasi-silicon-on-insulator metal-oxide semiconductor field-effect transistor with pi-shaped semiconductor conductive layer. According to the simulation results, we found that the short-channel characteristics and self-heating are much sensitive to the source/drain thickness. A reasonable explanation of the results is given. Furthermore, an ultra-thin silicon-on-insulator structure is also designed to be compared with the proposed structure.

An SOI-based self-aligned quasi-SOI MOSFET with π-shaped semiconductor conductive layer

This paper investigates the device behaviours of a pseudo tri-gate ultra-thin-channel vertical MOSFET with source/drain tie. For comparison two transistors are designed. According to the 2D simulation, our proposed structure can effectively enhance the drain current and the thermal stability, mainly due to the ultrathin channel (Tsi = 10 nm). The fabricated device have very low subthreshold swing near 60 mV/dec with channel length 40 nm to 90 nm and excellent GM of 4 mS/mum with channel length 35 nm owing to its unique features, when compared to its counterpart. Also, the respective discontinuous buried oxide under the channel and the source/drain regions can construct a natural source/drain tie to overcome short-channel effects and self-heating effects as well.