Yi-Chuen Eng

Characteristics of a new trench-oxide thin-film transistor and its 1T-DRAM applications

In this paper, we propose a simple trench-oxide thin-film transistor (TO TFT) process for 1T-DRAM applications. Our proposed TO TFT structure has several novel features as follows: 1. The buried oxide and the isolation oxide are carried out simultaneously in order to achieve a goal of simple process. 2. The trench design is used to improve both the sensing current windows (∼ 84%) and the retention time (∼ 57%). 3. The thermal stability is drastically improved by its naturally formed source/drain tie. The above mentioned features help our proposed device structure to demonstrate the desired characteristics that are better than that of a conventional TFT. Additionally, the thermal instability is drastically improved which is good for long-term device operation.

Novel Vertical SOI-Based 1T-DRAM With Trench Body Structure

A vertical silicon-on-insulator (VSOI)-based capacitorless 1T-DRAM cell with a trench body structure is proposed. The trench body is added as an additional neutral region under the device channel region through a self-aligned fabrication process in a 300 nm wide VSOI MOSFET that enables the device to separate the hole storage region and sense electron current region without extra area penalty. With the holes stored in the trench body, the floating-body effect occurs and affects the threshold voltage significantly. A Synopsys TCAD software tool is also used to evaluate the device performance for DC and transient analysis. The electrical and transient characteristics confirm how the proposed device with trench body can be used perfectly as a 1T-DRAM application to achieve desirable performance in terms of a larger programming window and longer retention time.

A novel high-performance junctionless vertical MOSFET produced on bulk-Si wafer

In this paper, we propose a junctionless vertical MOSFET (JLVMOS) based on bulk-Si wafer. According to the numerical simulations, the proposed JLVMOS can get a steep subthreshold swing (S. Swing), reduced DIBL, and higher ION/IOFF ratio, in comparison to a junctionless planar SOI MOSFET. This is because the vertical double-gate (DG) structure truly helps reduce the short-channel effects (SCEs). More importantly, SOI wafer is not necessary as a starting material for our proposed junctionless transistor, which is good for low-cost mass production.

Numerical Study of a Highly Scaled Bulk MOSFET With Block Oxide and Source/Drain-Tied Structure

In this paper, we present a highly scaled bulk metal-oxide-semiconductor field-effect transistor with block oxide (BO) and source/drain (S/D)-tied structure that meets the International Technology Roadmap for Semiconductors requirements for high-performance devices. This new device requires only a simple BO fabrication process using SiGe-Si epitaxial growth with selective SiGe removal and requires no additional lithography masks. This proposed BO fabrication process is simple due to it being controllable, repeatable, and fully compatible with standard complementary metal-oxide-semiconductor technology. According to 3-D simulations, our proposed structure not only exhibits its structural advantages to overcome scaling obstacles but also extends the use of planar bulk technology to the decananometer regime.

Short-Channel Characteristics of Self-Aligned

A novel device architecture-the self-aligned pi-shaped source/drain (S/D) ultrathin silicon-on-insulator (UTSOI) FET-is presented for the first time in the field of silicon-on-insulator (SOI) technology; this new device demonstrates how to decrease the self-heating effects in the SOI-based devices. Two-dimensional simulations show that the cost of building an S/D tie into the UTSOI-FET is a modest degradation of the short-channel characteristics including drain-induced barrier lowering (DIBL) and subthreshold swing (SS), when compared with a traditional UTSOI-FET. This degradation occurs because the S/D-tied scheme introduces two additional pathways between the S/D regions and the silicon substrate, thereby reducing the gates ability to control the channel. Yet, the results presented here show these negative effects to be reasonably small (e.g., DIBL ang 90 mV/V and SS ang 100 mV/dec), whereas the positive effect of reduced self-induced heating is substantial and significantly improves device reliability.

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In this paper, we propose a simple trench-oxide thin-film transistor (TO TFT) process for 1T-DRAM applications. Our proposed TO TFT structure has several novel features as follows: 1. The buried oxide and the isolation oxide are carried out simultaneously in order to achieve a goal of simple process. 2. The trench design is used to improve both the sensing current windows (∼ 72%) and the retention time (∼ 50%). 3. The thermal stability is drastically improved by its naturally formed source/drain tie. The above mentioned features help our proposed device structure to demonstrate the desired characteristics that are better than that of a conventional TFT. Additionally, the thermal instability is drastically improved which is good for long-term device operation.

-Shaped Source/Drain Ultrathin SOI MOSFETs

This paper presents a complementary Lubistor and TFET (CLTFET) inverter, which is composed of a lateral unidirectional bipolar-type insulated-gate transistor (Lubistor) load and a tunneling field effect transistor (TFET) driver. Based on the measurement data of Lubistor and TFET devices published, we have for the first time drawn the load lines and operation point line (Q line) of the new designed CLTFET compared with the conventional CTFET to verify its feasibility. The delay time is improved more than 29.5%. Additionally, due to its unique structure and the output node being shared by the load and the driver, the integration density of it can be reduced dramatically. The area benefit thus more than 32.6% has been achieved compared with the conventional CTFET layout.

A simple process of thin-film transistor using the trench-oxide layer for improving 1T-DRAM performance

In this paper, a new device structure called the quasi-SOI MOSFET with pi-shaped semiconductor conductive layer is proposed and demonstrated. In this structure, the pi-shaped source/drain layer is formed by the block oxide which consists of three separate oxide islands under the source, the drain, and the body regions, respectively. In other words, due to the three separate oxide islands forming two paths from source/drain to substrate, the generated holes and heat can be eliminated from this source/drain-tied scheme, thus, the proposed quasi-SOI structure shows to improve the kink effect and the self-heating problem as compared with that of conventional SOI structures. Moreover, owing to that the block oxide is utilized to restrict the electric field built between body and source/drain region, the ultra-short-channel effect is also diminished. Besides, our structure is based on the bulk wafer, thus, the cost can be cheaper than the SOI wafer

A new type of CMOS inverter with Lubistor load and TFET driver for sub-20 nm technology generation

In this paper, a vertical n-channel enhancement-type MOSFET with internal block layer (bVMOS) is investigated theoretically. In the proposed structure, the internal block layer comprises a buried block layer and a sidewall block layer. We also test three blocking materials (ex. doped Si, nitride and oxide) for performance comparisons. That is, the p-n junction region between the substrate and drain is isolated by the buried block layer thereby reducing the p-n junction leakage current and the parasitic capacitance. Similarly, the electrical field between the body and drain is blocked or shielded by the sidewall block layer; hence the intolerable ultra-short-channel effects, such as drain-induced barrier lowering (DIBL), hot-carrier effect, source/drain (S/D) punchthrough, and charge-sharing effect, are ameliorated tellingly. Owing to the suppression of the ultra-short-channel effects, excellent subthreshold swing is also successfully achieved by the nano-scale regime. Moreover, the proposed vertical structure has a path between the body and the substrate, the generated hole current by impact ionization and generated heat in channel can be banished from this pass way. Thus, both the floating-body effects and the self-heating effects are avoided synchronously

Elimination of Floating body Effect and Thermal Instability in a Nano Quasi-SOI MOSFET with π-shaped Semiconductor Layer

In this paper, we propose a novel fully depleted silicon-on-insulator MOSFET with block oxide enclosed body (bFDSOI). To differ with the conventional FDSOI MOSFET, the proposed SOI structure shows enhanced performance by exploiting sidewall spacer process. For this new bFDSOI device, the electric field between the body and the source/drain (S/D) region is restrained by the block oxide resulting in that the ultra-short-channel effects (USCEs) are suppressed. Thus, the simulation results of bFDSOI exhibit reduced drain-induced barrier lowering (DIBL), excellent subthreshold swing (SS), good roll-off characteristics and high drain output resistance for 40 nm thick enough body. In order to eliminate the floating-body problem, the bFDSOI device must not be operated under the partially depleted (PD) regime. Although this is the limit of device design, as the gate length is scaled down, the requirement of the ultra-thin body (UTB) structure is not needed to maintain its ultra-short-channel characteristics control over the channel due to the block oxide serves as isolation between the body and the S/D region. Moreover, owing to that the sufficient thick body is used; the bFDSOI device results in good amelioration of self-heating effects (SHEs), which is very important in a nano-scale SOI MOSFET design