Po-Hsieh Lin

Novel Vertical SOI-Based 1T-DRAM With Trench Body Structure

A vertical silicon-on-insulator (VSOI)-based capacitorless 1T-DRAM cell with a trench body structure is proposed. The trench body is added as an additional neutral region under the device channel region through a self-aligned fabrication process in a 300 nm wide VSOI MOSFET that enables the device to separate the hole storage region and sense electron current region without extra area penalty. With the holes stored in the trench body, the floating-body effect occurs and affects the threshold voltage significantly. A Synopsys TCAD software tool is also used to evaluate the device performance for DC and transient analysis. The electrical and transient characteristics confirm how the proposed device with trench body can be used perfectly as a 1T-DRAM application to achieve desirable performance in terms of a larger programming window and longer retention time.

A novel high-performance junctionless vertical MOSFET produced on bulk-Si wafer

In this paper, we propose a junctionless vertical MOSFET (JLVMOS) based on bulk-Si wafer. According to the numerical simulations, the proposed JLVMOS can get a steep subthreshold swing (S. Swing), reduced DIBL, and higher ION/IOFF ratio, in comparison to a junctionless planar SOI MOSFET. This is because the vertical double-gate (DG) structure truly helps reduce the short-channel effects (SCEs). More importantly, SOI wafer is not necessary as a starting material for our proposed junctionless transistor, which is good for low-cost mass production.

Numerical Study of a Highly Scaled Bulk MOSFET With Block Oxide and Source/Drain-Tied Structure

In this paper, we present a highly scaled bulk metal-oxide-semiconductor field-effect transistor with block oxide (BO) and source/drain (S/D)-tied structure that meets the International Technology Roadmap for Semiconductors requirements for high-performance devices. This new device requires only a simple BO fabrication process using SiGe-Si epitaxial growth with selective SiGe removal and requires no additional lithography masks. This proposed BO fabrication process is simple due to it being controllable, repeatable, and fully compatible with standard complementary metal-oxide-semiconductor technology. According to 3-D simulations, our proposed structure not only exhibits its structural advantages to overcome scaling obstacles but also extends the use of planar bulk technology to the decananometer regime.

Transient and Thermal Analysis on Disturbance Immunity for 4

This paper presents a one-transistor dynamic random access memory (1T-DRAM) based on a novel surrounding-gate transistor with wide trenched body (WT-SGT). This 1T-DRAM exhibits favorable transient performance after word line (WL)/bit line (BL) disturbance, which is verified using Sentaurus TCAD 12.0. The proposed memory cell can be fabricated with a feature area of 4F2 and with processes that are fully compatible with conventional CMOS technology. Extended simulations reveal three key findings. First, the WT-SGT achieves a high-speed programming operation (1.17 ns) at a low operating voltage (1.6 V) and with a programming window that can be further extended by widening its trenched body. Second, the recombination rate is also reduced, thereby yielding an acceptable retention time (RT) of 625.6 ms. Third, the decreased RT after a 100-ns WL/BL disturbance is improved by 33%, as compared with a conventional SGT 1T-DRAM. We, therefore, believe that this new device will become a competitive candidate for use in future DRAM cells.

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A novel device architecture-the self-aligned pi-shaped source/drain (S/D) ultrathin silicon-on-insulator (UTSOI) FET-is presented for the first time in the field of silicon-on-insulator (SOI) technology; this new device demonstrates how to decrease the self-heating effects in the SOI-based devices. Two-dimensional simulations show that the cost of building an S/D tie into the UTSOI-FET is a modest degradation of the short-channel characteristics including drain-induced barrier lowering (DIBL) and subthreshold swing (SS), when compared with a traditional UTSOI-FET. This degradation occurs because the S/D-tied scheme introduces two additional pathways between the S/D regions and the silicon substrate, thereby reducing the gates ability to control the channel. Yet, the results presented here show these negative effects to be reasonably small (e.g., DIBL ang 90 mV/V and SS ang 100 mV/dec), whereas the positive effect of reduced self-induced heating is substantial and significantly improves device reliability.

Surrounding Gate 1T-DRAM With Wide Trenched Body

This paper presents a complementary Lubistor and TFET (CLTFET) inverter, which is composed of a lateral unidirectional bipolar-type insulated-gate transistor (Lubistor) load and a tunneling field effect transistor (TFET) driver. Based on the measurement data of Lubistor and TFET devices published, we have for the first time drawn the load lines and operation point line (Q line) of the new designed CLTFET compared with the conventional CTFET to verify its feasibility. The delay time is improved more than 29.5%. Additionally, due to its unique structure and the output node being shared by the load and the driver, the integration density of it can be reduced dramatically. The area benefit thus more than 32.6% has been achieved compared with the conventional CTFET layout.

Short-Channel Characteristics of Self-Aligned

This paper for the first time presents a performance comparison between junction and junctionless thin-film transistors (TFTs) by using TCAD simulations. Note that the DIBL and S.S. of a junctionless TFT (JLTFT) are larger and higher, respectively, than those of its junction TFT (JTFT) counterpart. Although the JLTFT gets a higher current drive based on the same Vov as compared with the JTFT, its short-channel characteristics are worse and degraded. These results can be attributed to the fact that the major carriers in channel region for a JTFT make itself a barrier to carrier scattering, whereas, the JTFT does not have this problem, leading to get a high current drive. On the other hand, it may be owing to the grain boundary effects for a JLTFT to degrade its short-channel behavior. Fortunately, these results are still acceptable for scaled dimensions of TFTs.

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One-transistor dynamic random access memory (1T-DRAM) thin-film transistor (TFT) could lead the revolution of system-on-panel application. However, no useful 1T-DRAM is fabricated on the polysilicon (poly-Si) thin film up to now. In this letter, we present a novel method to fabricate a smiling poly-Si TFT for 1T-DRAM applications. The experimental results show that the short-channel effects can be reduced because the smiling scheme is used to suppress the charge sharing and the source/drain-tied scheme can help to overcome the self-heating. Moreover, the device fabrication is fully compatible with current complementary metal-oxide-semiconductor (CMOS) technology.

-Shaped Source/Drain Ultrathin SOI MOSFETs

In this paper, we propose a new Voltage- programming pixel circuit using hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) for an active matrix organic light-emitting diode (AMOLED). The proposed a-Si:H TFT pixel circuit, which consists of four p-type switching TFTs, one n-type driving TFT, two additional control signals and one storage capacitor, successfully compensated the OLED current fluctuation caused by threshold voltage shift of a-Si:H TFT and the drop on the supply voltage, the propose pixel circuit has been verified by the simulation work using HSPICE software, the simulation result show that this pixel circuit has high immunity to the variation of a-Si:H TFT characteristics.

A new type of CMOS inverter with Lubistor load and TFET driver for sub-20 nm technology generation

This paper aims to comprehensively examine the electrical characteristics of a new silicon-on-insulator (SOI) device structure with source/drain (S/D) tie as a function of the block oxide height. According to the 2-D simulations, the height of the block oxide enclosing the silicon body is one of the key parameters for determining the device properties and their fluctuations. Additionally, the self-heating effects (SHEs) can be well controlled chiefly due to the presence of the S/D-tied scheme.