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Featured researches published by Shigeyuki Murai.


Complete Guide to Semiconductor Devices, Second Edition | 2012

Schottky barrier diode

Tetsuro Asano; Katsuaki Onada; Yoshibumi Nakajima; Shigeyuki Murai; Hisaaki Tominaga; Koichi Hirata; Mikito Sakakibara; Hidetoshi Ishihara

In the central region of the substrate, is formed adjacent to the second semiconductor layer and second semiconductor layer adjacent to the guard ring across a third insulating layer between the second semiconductor layer. I.e., between the second semiconductor layer and the second semiconductor layer, forming a third insulating layer covering the first semiconductor layer on the first surface of the substrate (the main surface) is exposed. Thus, the third insulating layer between the second semiconductor layer and the second semiconductor layer, the electrical insulation between the first semiconductor layer and the metal layer of the substrate first face 11a 11 exposed.


GaAs IC Symposium Technical Digest 1992 | 1992

A high power-added efficiency GaAs power MESFET operating at a very low drain bias for use in L-band medium-power amplifiers

Shigeyuki Murai; Tetsuro Sawai; Tsutomu Yamaguchi; Shigeharu Matsushita; Yasoo Harada

A power MESFET offering a high eta /sub add/ operating at a very low V/sub DD/ has been developed. The MESFET has a buried p-layer and an improved LDD (lightly doped drain) n+ self-aligned structure which include highly electrically activated ion-implanted regions due to rapid thermal-cap annealing using double-layered SiN films deposited by ECR plasma chemical vapor deposition. The device geometries and implantation conditions were optimized to achieve a high V/sub (BR)GDO/ of more than 10 V and a low V/sub K/ of less than 0.5 V, and to minimize the bias dependence of S-parameters. This produced excellent electrical characteristics such as P/sub 0(1dB/)=177 mW (173 mW), eta /sub add/=38.8% (32.6%) at V/sub DD/=3 V (2 V), and I/sub DS/=0.16 A ( approximately 0.4I/sub DSS/) (0.24 A ( approximately 0.6I/sub DSS/)) at 1.9 GHz.<<ETX>>


international microwave symposium | 1998

A high efficiency GaAs power amplifier module with a single voltage for digital cellular phone systems

Masao Nishida; Shigeyuki Murai; Hisanori Uda; Hisaaki Tominaga; Tetsuro Sawai; Akira Ibaraki

This work describes a two-stage 0.2 cc power amplifier (PA) module with single voltage operation for digital cellular phone system terminals. A new GaAs FET structure enables this operation. To increase power-added efficiency, it is found to be advantageous to use heat spreading with a Cu plate in the cavity and second-order harmonic suppression with the trap capacitor built into the drain bias circuit. Output power of 30.5 dBm with power added efficiency of 54% has been obtained at 1.45 GHz and 3.5 V.


international microwave symposium | 1999

A novel design concept for a super compact power amplifier module (SCPAM) using a multilayer substrate

Masao Nishida; Shigeyuki Murai; S. Banba; T. Yamaguchi; Tetsuro Sawai; M. Sawada

This paper presents a novel circuit and layout design concept for a Super Compact Power Amplifier Module (SCPAM) using a multilayer substrate. This concept enables miniaturization of the module, while continuing to allow easy design and good performance. A 0.04 cc 1 W class module for mobile communication systems is demonstrated. A 0.02 cc module including this concept is also proposed.


international microwave symposium | 1996

A super low-noise ion-implanted planar GaAs MESFET MMIC amplifier

Tetsuro Sawai; Masao Nishida; Toshikazu Hirai; K. Honda; T. Yamaguchi; Shigeyuki Murai; Yasoo Harada

In order to develop an ultra-compact and super low-noise MMIC amplifier for the receiving system of PHS, the input and output impedance of an ion-implanted planar GaAs MESFET were successfully reduced while maintaining its high-gain and low-noise characteristics. The MMIC had a noise figure of 1 dB and a gain of 13.5 dB at 3 V, 20 mA and 1.9 GHz in an ultra-compact plastic package. The fabricated switch and LNA module employing this MMIC has achieved the low-noise property of less than 3 dB.


Archive | 1994

Method of designing a high-frequency circuit

Tetsuro Sawai; Shigeyuki Murai; Tsutomu Yamaguchi; Yasoo Harada


Archive | 1992

High-breakdown voltage field-effect transistor

Shigeyuki Murai; Takayoshi Higashino; Masao Nishida


Archive | 2003

Field effect transistor semiconductor and method for manufacturing the same

Shigeyuki Murai; Emi Fujii; Shigeharu Matsushita; Hisaaki Tominaga


Archive | 2002

Manufacturing method of schottky barrier diode

Tetsuro Asano; Katsuaki Onoda; Yoshibumi Nakajima; Shigeyuki Murai; Hisaaki Tominaga; Koichi Hirata; Mikito Sakakibara; Hidetoshi Ishihara


Archive | 2002

Integrated schottky barrier diode and manufacturing method thereof

Tetsuro Asano; Katsuaki Onoda; Yoshibumi Nakajima; Shigeyuki Murai; Hisaaki Tominaga; Koichi Hirata; Mikito Sakakibara; Hidetoshi Ishihara

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