Yu-Che Yang

A Quantization Noise Suppression Technique for

The first circuit implementation of quantization noise suppression technique for DeltaSigma fractional- N frequency synthesizers using reduced step size of frequency dividers is presented in this paper. This technique is based on a 1/1.5 divider cell which can reduce the step size of the frequency divider to 0.5 and thus the reduced step size suppresses the quantization noise by 6 dB. This frequency synthesizer is intended for a WLAN 802.11a/WiMAX 802.16e transceiver. This chip is implemented in a 0.18-mum CMOS process and the die size is 1.23 mm times 0.83 mm. The power consumption is 47.8 mW. The in-band phase noise of -100 dBc/Hz at 10 kHz offset and out-of-band phase noise of -124 dBc/Hz at 1MHz offset are measured with a loop bandwidth of 200 kHz. The frequency resolution is less than 1 Hz and the lock time is smaller than 10 mus

DeltaSigma

A low-voltage (0.5 V) and low-power (4.535 mW) monolithic biomedical system-on-a-chip (SOC) consisting of a receiver, a transmitter, a microcontrol unit, and an analog-to-digital converter (ADC), implemented in a 0.18-μm CMOS technology for intrabody communication is first reported. The SOC can take command through a human body and activate (or turn on) the ADC and transmitter inside the SOC. Then, a biomedical signal is converted to digital format and transmitted to the RF gateway through a human body. With this transmission methodology and the proposed SOC circuit, it is much more power efficient than wireless communication. Moreover, since no antenna is required, the chip size of the SOC is only 1.5 mm2, excluding the test pads.

Fractional-

A quick (<30min.), label-free detection of disease-related C-reactive proteins (CRP) is achieved using a 200mum MEMS microcantilever housed in a 7times7mm2 reaction chamber. The deflection of the cantilever due to specific CRP/anti-CRP binding is detected using a position-sensitive photodiode and the converted bio-signal is transmitted by a wireless ASK transceiver IC fabricated in a 0.18mum CMOS process. CRP concentrations from 1mug/mL to 500mug/mL can be detected. A 0.2Hz 1V ac signal is applied to the bio-MEMS sensor to unbind CRP from the cantilever for reuse

N

A divide-by-1/1.5 divider cell using a dual edge-trigger technique is proposed. Based on this divider cell, a dual-mode programmable divide-by-X circuit is demonstrated in 0.18-/spl mu/m CMOS technology, where X=P or P.5 in one mode and 2P or 2P+1 in the other mode with P=128-255. When operated in the divide-by-2P/2P+1 mode, this circuit outputs a signal with 50% duty cycle. Theoretically, P can be any arbitrary and programmable integer.

Frequency Synthesizers

The availability of unlicensed mm-wave bands has fueled the research and development of mm-wave wireless systems. If different frequency bands can be operated from one signal source, it will reduce the circuit size and power consumption, leading to compact systems. For example, the frequencies 38, 57, 76GHz in 38, 60 and 77GHz bands can be generated by using only one PLL, as illustrated in Fig. 16.4.1. To address this requirement, in this paper, a multiband multimode injection-locked frequency divider (M-ILFD) is presented that meets the requirements for 38 and 57GHz applications.

A 0.5-V Biomedical System-on-a-Chip for Intrabody Communication System

A 5.0-GHz-band monolithic direct-conversion receiver front end employing subharmonic mixers (SHMs) is demonstrated in 0.18-mum CMOS technology. Instead of using transistors as transconductors, the SHMs adopt on-chip 1:4 transformers to achieve voltage gain, and hence, excellent local-oscillator self-mixing suppression and good linearity can be obtained. Additionally, a CMOS-compatible postprocess is used to selectively remove the silicon substrate underneath the inductors and transformers of the receiver front end. While dissipating 43.9 mW from a 1.8-V supply, the micromachined receiver front end exhibits a voltage gain of 28.0 dB, a noise figure of 9.7 dB, a third-order input intercept point of -7.8 dBm at 5.0 GHz, and an input-referred dc offset of -118.0 dBm. The proposed receiver front end is further integrated with analog baseband circuits, a fractional-N frequency synthesizer, and a serial-to-parallel data converter to accomplish a multioperation-mode receiver.

A Wireless Bio-MEMS Sensor for C-Reactive Protein Detection Based on Nanomechanics

A new input matching method making use of shunt-shunt feedback capacitance is introduced. Based on the new input matching method, reconfigurable SiGe low-noise amplifiers (LNAs) by varying shunt-shunt feedback capacitance are proposed. Two approaches are used to vary the shunt-shunt feedback capacitance. One approach is to switch between two different bias currents while the other is to use a series combination of a switch and a capacitor. Miniaturized fully monolithic reconfigurable SiGe LNAs without emitter degenerative inductors were realized by the above two approaches. The reconfigurable SiGe LNA achieved by switching bias currents only occupies a very small area of 355 mumtimes155 mum, excluding measurement pads. This LNA achieves an input return losses (S11) of -27.6 dB, a voltage gain (A v) of 19.8 dB, and a noise figure (NF) of 3.18 dB for 2.4-GHz band when biased at a current of 3.8 mA and can be reconfigured to obtain Av=20.4/20.3 dB, S11=-47.1/-24.6 dB and NF=3.42/3.21 dB for 5.2/5.7-GHz band when bias current is switched to 3 mA. In addition, a 2.4/4.9/5.2/5.7-GHz reconfigurable SiGe LNAs for WLAN applications, whose variable shunt-shunt feedback capacitance is controlled by a switch and a capacitor, was also realized

A dual-mode truly modular programmable fractional divider based on a 1/1.5 divider cell

A single-VCO fractional-N frequency synthesizer is designed for DVB-T and ISDB-T Digital TV tuners. This frequency synthesizer architecture can cover all the frequency bands for both standards with only one VCO and thus the chip area as well as the power consumption can be greatly reduced. The synthesizer was fabricated in a 0.18 mum CMOS process with a 2.2 V power supply and occupies an area of 1.5 mm2. The loop bandwidth is 300 kHz and the total setting time is smaller than 70 mus.

A mm-wave CMOS multimode frequency divider

A single-voltage-controlled-oscillator (VCO) fractional-N frequency synthesizer is designed for Advanced Television Systems Committee, Digital Video Broadcasting-Terrestrial, and Integrated Services Digital Broadcasting-Terrestrial digital television tuners. This frequency synthesizer can cover all the frequency bands for all three standards with only one VCO, and thus, the chip area as well as the power consumption can be greatly reduced. Different channel spacing requirements can be fulfilled by fractional synthesis. A dynamic frequency calibration loop is also used to automatically choose the coarse setting of the VCO. The synthesizer was fabricated in a standard 0.13-μm complementary metal-oxide-semiconductor process and draws 14 mA from a 1.2-V supply. The measured phase noise is lower than -80 dBc/Hz from 1 to 100 kHz offset and -100 dBc/Hz at 1 MHz offset. The active area of the frequency synthesizer is smaller than 0.54 mm2.

A 5-GHz-Band CMOS Receiver With Low LO Self-Mixing Front End

A ΔΣ fractional-N frequency synthesizer with a quantization noise pushing technique is implemented in a 0.18 mum CMOS technology. The in-band phase noise can be lowered by 12 dB, and the out-band phase noise contributed by the ΔΣ modulator can be reduced by more than 15 dB with this technique. The power consumption is 26.8mW from a 2V supply.