Shikayuki Ochi

Thermal stability and secondary breakdown in planar power MOSFET's

The destructive secondary-breakdown mechanism of high-voltage n-channel power MOSFETs is discussed. A model is proposed in which the secondary breakdown is caused primarily by the negative-resistance effects of a parasitic bipolar transistor structure. The model suggests that destructive breakdown can be suppressed by a new no-surface-breakdown structure fabricated on a p-on p+epitaxial wafer. Power MOSFETs having this structure have been realized and are completely free from secondary breakdowns, as suggested by the model. In addition, experimental evidence for excellent thermal stability of the power MOSFET is given by infrared scanner measurements of the temperature rise in the chip compared with bipolar transistors. An n-channel planar power MOSFET with a 400-W power limitation at 220-V breakdown voltage and a maximum current of 12 A has been successfully fabricated.

A complementary pair of planar-power MOSFET's

A complementary pair of planar-power MOSFETs has been developed, each of which has drain breakdown voltage as high as 250 V and 12-A current capability. These devices have field plates on the ion-implanted gate offset region to realize high-breakdown voltages and large current capabilities. The field distribution behavior of a field-plated high-voltage MOSFET and a non-field-plated device are compared. In this procedure, the first-order theory of pinchoff voltage of the offset region, the most important parameter for a planar-power MOSFET, is derived for high-voltage and high-current capability design. Experimental results to support the usefulness of a field plate for improving breakdown voltage and current capabilities are obtained and discussed. Finally, future possible developments of these devices, such as high-voltage and high-current approaches, are described and a new type of device structure is proposed.

A complementary-pair of high-power MOSFET's

A complementary pair of high power MOSFETs is developed, each of which has a drain breakdown voltage as high as 200V and 10A current capabilities. This device has an offset gate and an ion-implanted additional channel to realize this high breakdown voltage. The device structure including the use of a field plate, is optimized by two dimensional MOS analysis. This design and a highly refined polysilicon gate fabrication process contribute to the realization of the high power devices. Measurement of these devices reveals superior thermal characteristic and assures a larger ASO than that of conventional bipolar transistors of the same chip size.

100 Watt Super Audio Amplifier Using New Mos Devices

A 100 watt audio amplifier was recently developed using a new Power MOSFET which was developed by our MOS Device Group. The Power MOSFET has several advantages over bipolar transistors. It has good frequency response, no carrier storage delay, thermal stability, no secondary breakdown and high input impedance.

Computer analysis of breakdown mechanism in planar power MOSFET's

Breakdown mechanism in planar power MOSFETs having high breakdown voltage is investigated. Precise electric field distribution is obtained by two-dimensional numerical analysis. This field distribution is used to optimize device structure and to predict breakdown voltage. A technique for reducing the electric field on the silicon surface by equalizing its distribution is presented.

A High Power MOS-FET with a Vertical Drain Electrode and Meshed Gate Structure

A p-channel power MOS-FET is developed which exhibits 20A current, 3\mho transconductance and 85 V breakdown voltage in a 5×5 mm2 chip. The features of the device structure are a vertical drain electrode which enables to use most of the surface area for the source electrode and a meshed gate structure which makes it possible for the channel width per unit area to become twice as large as that of a conventional MOS-FET, thereby drain current of the device can be increased. The device with an offset gate structure was fabricated from an n on p+ epitaxial wafer by using the polysilicon gate and the ion implantation processes. The device does not show local current concentration, thermal runaway or second breakdown. Stable operation is obtained at ambient temperatures up to 180°C, which is attributed to a negative temperature coefficient of the drain current.

A high power MOSFET with a vertical drain electrode and meshed gate structure

A power MOSFET is developed which exhibits 20A current, 3000mΩ transconductance and 85V breakdown voltage in a 5×5mm2chip. The features of the device structure are a vertical drain electrode which enables to use most of the surface area for the source electrode and a mesh gate structure which makes able to increase the channel width per unit area, thereby drain current of the device can be increased. The P-channel device with an offset gate structure was fabricated from an N on P+epitaxial wafer by using the polysilicon gate and the ion implantation processes. The device can be operated stably at ambient temperatures up to 180°C.

1/f Temperature Fluctuations in Solids

We propose a 1/f temperature fluctuation model, based on the random walk of a phonon in solids. When the phonon reaches the boundary of the solid, it is absorbed by the boundary. Thus, the statistical characteristics of the absorbed phonon follow the Poisson counting process, i.e., the flow variance of the absorbed phonon is given by the average phonon flow. This relationship gives a 1/f fluctuation spectrum on the phonon density fluctuation that generates a 1/f temperature fluctuation. Using this relationship, we calculated a 1/f fluctuation in the resistors. The resulting power spectrum was about one tenth of the value reported by Voss, and the calculated Hooge’s constant was around one fourth of the reported value. These quantitative and qualitative coincidences support our 1/f temperature fluctuation model.

Short Channel, Low Noise UHF MOS-FET's Utilizing Molybdenum-Gate Masked Ion-Implantation

A low noise high cutoff frequency dual-gate MOS-FET with a Mo-gate is fabricated using gate-masked ion-implantation. In the high frequency region, low noise performance is achieved with a short channel and minimum resistive parasitics such as gate and source resistances. To reduce the effect of the gate resistance, a new comb type structure with low resistive Mo film is realized. The dual-gate FET with a channel length of 1.3 µ as the 1st channel and 2.5 µ as the 2nd channel, a channel width of 1.2 mm and a gate oxide thickness of 600 A, was operated at 800 MHz with a minimum noise figure of 2.4 dB and a power gain of 19 dB. Good cross modulation characteritic was also confirmed.