Mamoru Ugajin

A 1-V 2.4-GHz PLL synthesizer with a fully differential prescaler and a low-off-leakage charge pump

A 1 V 2.4 GHz-band fully monolithic PLL synthesizer was fabricated using 0.2 /spl mu/m CMOS/SOI process technology. It includes a voltage controlled oscillator (VCO) and a 3 GHz fully differential dual-modulus prescaler on a chip. A low-off-leakage-current charge pump is used for open-loop FSK modulation. When the PLL is in open loop mode, the frequency drift of the output is lower than 2.5 Hz//spl mu/sec. The output phase noise is -104 dBc/Hz at 1 MHz offset frequency. The power consumption of the PLL-IC core is 17 mW at 1 V supply voltage.

Nano-watt power management and vibration sensing on a dust-size batteryless sensor node for ambient intelligence applications

Nanowatt-power circuit techniques that could overcome the critical bottlenecks preventing the realization of dust-size battery-less sensor nodes are reported. Sensor networks deploying large numbers of nodes are anticipated for “ambient intelligence” [1]. For such networks, the sensor nodes should be miniaturized to the size of dust and be maintenance-free because battery-powered matchbox-sized nodes would be difficult to distribute in large numbers (100 to 1000, for instance) in rooms, and replacing the batteries would be very time-consuming. When the size of a power source is miniaturized to a few mm3, generated power is lowered to the nano-watt-level according to energy density limitations [2]. When the generated power is smaller than the power used for radio, sensor nodes have to accumulate energy [1]. The basic concept of a sensor node with functions for energy accumulation is shown in Fig. 27.10.1. The node contains the function blocks for power generation, power management, sensing, and radio. The power-management block accumulates energy to the accumulation capacitor, which is large enough for radio. When the voltage monitor detects that the voltage of the accumulated energy has reached the voltage needed for radio, the sensing block is activated. Then, the radio block transmits the sensed data when an event occurs. In this mode of operation, the voltage monitor for controlling the switch should operate with sub-nanowatt-level power dissipation because the monitor operates continuously during energy accumulation. Moreover, the power for sensing needs to be reduced to the sub-nanowatt level since the sensing function needs to be active after energy accumulation. On the other hand, the previous works for capacitive-sensing [3–4] and voltage reference [5] consume more than sub-microwatt since they use amplifiers and DC-biased resistors. To solve these problems, we use a voltage-monitoring circuit for power management and a vibration-sensing circuit that can operate even when the power source generates only nanoampere-level currents.

Macromodels in the frequency domain analysis of microwave resonators

This paper describes a 1-V operation Bluetooth RF transceiver in 0.2-/spl mu/m CMOS SOI. The transceiver integrates a radio-frequency transmit/receive switch, an image-reject mixer, a quadrature demodulator, g/sub m/-C filters, an LC-tank voltage-controlled oscillator, a phase-locked loop synthesizer, and a power amplifier. The phase shifter in the quadrature demodulator is tuned dynamically to track the carrier-frequency drift allowed in the Bluetooth specification. The g/sub m/ cell in the filters uses depletion-mode pMOS transistors. In order to achieve 1-V operation, LC-tuned-folded and transistor-current-source-folded circuits are used in the RF and IF building blocks, respectively. In order to minimize power consumption, the current flowing through the circuit is optimally shared between the folded stages. A tuning circuit for the g/sub m/-C filters and a bias generation circuit ensure stable transceiver performance. The transceiver shows -77-dBm sensitivity at 0.1% bit error rate and consumes 33 and 53 mW from 1 V in the transmit and receive modes, respectively.

Design techniques for a 1-V operation Bluetooth RF transceiver

This paper describes circuit techniques for a 1-V operation Bluetooth PF transceiver in 0.2-/spl mu/m CMOS/SOI. Folded LC-tuned and folded transistor-current-source circuits achieve 1-V operation of the RF transceiver. Tuning circuits and a bias generation circuit for robust transceiver operation are explained.

A 1-V CMOS/SOI bluetooth RF transceiver for compact mobile applications

A Bluetooth RF transceiver in 0.2-/spl mu/m CMOS/SOI achieves 1-V operation and paves the way for further system-size reduction by using a small NiH battery. The transceiver integrates a T/R switch, an image-reject mixer, a quadrature demodulator, gm-C filters, an LC-tank voltage-controlled oscillator, a PLL, and a power amplifier. The phase shifter in the quadrature demodulator is tuned dynamically to deal with carrier-frequency drift. A gm cell in the filters uses depletion-mode PMOS transistors and has a folded structure. The transceiver shows -77-dBm sensitivity at 0.1% BER.

A 5 th -order switched-capacitor complex filter for low-IF narrowband wireless receivers

A 5th-order switched-capacitor (SC) complex filter is implemented in 0.2-µm CMOS technology. In order to reduce the die size and current consumption of the complex filter, a novel SC integrator is developed. The filter is centered at 24.8 kHz with bandwidth of 20.2 kHz. The Image channel is attenuated by more than 40 dB. The in-band 3rd order harmonic input intercept point (IIP3) is 15 dBm and the in-band output noise is 70 µVrms. The complex filter consumes 350 µA with a 2.0-V power supply. The die size of the fabricated filter is 0.578 mm2. Owing to the proposed SC integrator, the fabricated filter achieved 27% reduction in die size without any characteristic degradation, including noise performance, compared to the conventional equivalent.

A 1-Mbps 1.6-μA Micro-power Active-RFID CMOS LSI for the 300-MHz Frequency Band

A micro-power active-RFID LSI with an all-digital RF-transmitting scheme achieves experimental 10-m-distance communication with a 1-Mbps data rate in the 300-MHz frequency band. The IC consists of a RF transmitter and a power-supply circuit, which controls the energy flow from the battery to the IC, and offers intermittent operation of the RF transmitter. The IC draws 1.6 μA from a 3.4-V supply and is implemented in a 0.2-μm CMOS in an area of 1 mm2. The estimated lifetime of the IC is over ten years with a micro-size battery.

A 1 V 12 mW 2 GHz receiver with 49 dB image rejection in CMOS/SIMOX

One of the most effective ways of reducing power is to minimize the supply voltage, and the LC-tuned folded mixer is one way to achieve this. For cost reduction, a fully-integrated image-rejecting receiver, i.e. one for which off-chip filters are not required, is a desirable target. A double-quadrature downconverter is usually used to provide sufficient image rejection because the signal is transformed so that gain mismatches and phase errors in the converter inputs are reduced to second-order at the converter outputs. However, the double-quadrature architecture consumes much power because six mixers are used. In spite of its single-quadrature architecture, this 2 GHz receiver suppresses phase errors in LO signals and achieves 49 dB image rejection without trimming.

Synchronized Multiple-Array Vibrational Device for Microelectromechanical System Electrostatic Energy Harvester

In this paper, we describe a novel structure of a vibrational micro-electro-mechanical system (MEMS) device for power generation enhancement. A synchronized multiple-array vibrational device, in which movable plates are connected by rods, increases the area of the movable plate in the energy conversion region and couples the phase of movement. The fabricated device resonates at approximately 1430 Hz with an acceleration amplitude of 6 m/s2 and nanoampere-order AC current is generated. These results confirm that this MEMS vibrational device will contribute to the progress in energy harvesting.

A 280-MHz CMOS intra-symbol intermittent RF front end for adaptive power reduction of wireless receivers

For adaptive reduction of power consumed by wireless receivers, we developed the first intra-symbol intermittent (ISI) RF front-end with 0.35-µm CMOS technology. In the demodulation mechanism, the RF output of the LNA is down-converted to an IF by the mixer, and the LNA and mixer operate synchronously and intermittently within a single symbol-length. Because the ISI frequency is low and the impedance-matching condition is maintained, the demodulation can be performed with low power. We experimentally demonstrate that demodulation (BPSK: 9.6 kbps) can be achieved with no intermodulation, where the intermittent operations ratio (IOR) is 12 %. This ISI operation of the RF front end is enabled by a newly devised fast-transition LNA and mixer. A theoretical analysis of thermal-noise aliasing in the RF ISI circuit reveals that RF ISI operation is more useful for the adaptive power reduction than current control (CC) in an RF front-end with continuous operation and that when the IOR is about 10 %, RF ISI operation is most effective and the NF is 1.2 dB lower than with RF CC.