Takakuni Douseki

1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS

1-V power supply high-speed low-power digital circuit technology with 0.5-/spl mu/m multithreshold-voltage CMOS (MTCMOS) is proposed. This technology features both low-threshold voltage and high-threshold voltage MOSFETs in a single LSI. The low-threshold voltage MOSFETs enhance speed performance at a low supply voltage of 1 V or less, while the high-threshold voltage MOSFETs suppress the stand-by leakage current during the sleep period. This technology has brought about logic gate characteristics of a 1.7-ns propagation delay time and 0.3-/spl mu/W/MHz/gate power dissipation with a standard load. In addition, an MTCMOS standard cell library has been developed so that conventional CAD tools can be used to lay out low-voltage LSIs. To demonstrate MTCMOSs effectiveness, a PLL LSI based on standard cells was designed as a carrying vehicle. 18-MHz operation at 1 V was achieved using a 0.5-/spl mu/m CMOS process. >

A 0.5-V 25-MHz 1-mW 256-kb MTCMOS/SOI SRAM for solar-power-operated portable personal digital equipment - sure write operation by using step-down negatively overdriven bitline scheme

Multithreshold-voltage CMOS (MTCMOS) technology has a great advantage in that it provides high-speed operation with low supply voltages of less than 1 V. A logic gate with low-V/sub th/ MOSFETs has a high operating speed, while a low-leakage power switch with a high-V/sub th/ MOSFET eliminates the off-leakage current during sleep time. By using MTCMOS circuits and silicon-on-insulator (SOI) devices, the authors have developed a 256-kb SRAM for solar-power-operated digital equipment. A double-threshold-voltage MOSFET (DTMOS) is adopted for the power switch to further reduce the off leakage. As regards the SRAM core design, we consider a hybrid configuration consisting of high-V/sub th/ and low-V/sub th/ MOSFETs (that is, multi-V/sub th/ CMOS). A new memory cell with a separate read-data path provides a larger readout current without degrading the static noise margin. A negatively overdriven bitline scheme guarantees sure write operation at ultralow supply voltages close to 0.5 V. In addition, a charge-transfer amplifier integrated with a selector and data latches for intrabus circuitry are installed to enhance the operating speed and/or reduce power dissipation. A 32K-word /spl times/ 8-bit SRAM chip, fabricated with the 0.35-/spl mu/m multi-V/sub th/ CMOS/SOI process, has successfully operated at 25 MHz under typical conditions with 0.5-V (SRAM core) and 1-V (I/O buffers) power supplies. The power dissipation during sleep time is less than 0.4 /spl mu/W and that for 25-MHz operation is 1 mW, excluding that of the I/O buffers.

A 0.5-V MTCMOS/SIMOX logic gate

This paper proposes a multithreshold CMOS (MTCMOS) circuit that uses SIMOX process technology. This MTCMOS/SIMOX circuit combines fully depleted low-threshold CMOS logic gates and partially depleted high-threshold power-switch transistors. The low-threshold CMOS gates have a large noise margin for fluctuations in operating temperature in addition to high-speed operation at the low supply voltage of 0.5 V. The high-threshold power-switch transistor in which the body is connected to the gate through the reverse-diode makes it possible to obtain large channel conductance in the active mode without any increase of the leakage current in the sleep mode. The effectiveness of the MTCMOS/SIMOX circuit is confirmed by an evaluation of a gate-chain test element group (TEG) and an experimental 0.5-V, 40-MHz, 16-b ALU, which were designed and fabricated with 0.25-/spl mu/m MTCMOS/SIMOX technology.

A wireless self-powered urinary incontinence sensor system

A self-powered urinary incontinence sensor system consisting of a disposable urine-activated coin battery and a wireless transmitter has been developed as an application for wireless sensor networks. The urine-activated battery makes possible both the sensing of urine leakage and self-powered operation. An intermittent power-supply circuit that uses an electrical double-layer capacitor (EDLC) with a small internal resistance suppresses the supply voltage drop due to the large internal resistance of the battery. This circuit and a 1-V SAW oscillator reduce the power dissipation of a wireless transmitter. The SAW oscillator quickly responds to the on-off control of the power supply, which makes it suitable for intermittent operation. To verify the effectiveness of the circuit scheme, we fabricated a prototype sensor system. When the volume of urine is 0.2 ml, the battery outputs a voltage of over 1.3 V; and the sensor system can transmit signals over a distance of 50 cm.

A 0.5-1 V MTCMOS/SIMOX SRAM macro with multi-V/sub th/ memory cells

Summary form only given. Sub-1 V CMOS circuit technology on ultrathin-film SOI is the most effective candidate for ultralow-power applications in future ULSIs. We have proposed various multi-threshold CMOS/SIMOX (MTCMOS/SIMOX) circuits (Douseki et al., 1996; Fujii et al., 1998) that operate at an ultralow supply voltage down to 0.5 V. Combining fully-depleted low-V/sub th/ CMOS logic gates and partially-depleted high-V/sub th/ power-switch transistors makes it possible to achieve high-speed and low-power operation in both the active and the sleep mode. Using MTCMOS/SIMOX technology, we have developed various sub-1 V digital LSIs (Douseki et al., 1998; Fujii et al., 1999). However, it has been difficult to apply MTCMOS/SIMOX technology to SRAM. This is because a memory cell has to be composed of high-V/sub th/ MOSFETs to store data in the sleep mode. The high-V/sub th/ cells and the read-out circuit around them disturb high-speed and low-power operation of the SRAMs. Low-voltage SOI memories (Shahidi et al., 1993; Shimomura et al., 1997) that operated at a supply voltage of around 1 V have been reported, but there are no ultralow-voltage memories that operate at supply voltages down to 0.5 V. In this paper, we describe a multi-V/sub th/ memory cell that performs high-speed read operation at low-V/sub th/ MOSFETs and a high-V/sub th/ charge-transfer-type multiplexer that makes possible high-speed and low-power operation for large capacity SRAMs with large bit-line capacitance.

Practical High-Resistivity Silicon-on-Insulator Solution for Spiral Inductors in Radio-Frequency Integrated Circuits

The effect of high-resistivity (high-R) silicon-on-insulator (SOI) substrates on spiral inductors in radio-frequency integrated circuits (RF ICs) has been investigated by experiment and simulation. The effect of the high-R substrates on the spiral inductors saturates at a resistivity above 2–3 kΩ cm, and the resistivity must be maintained high with a thickness of about 300 µm. The resistivity dependence of the high-R effect can be explained with a dielectric loss mechanism in silicon substrates. The thickness criterion of the effect can be explained with an inductor model that includes magnetically induced current in a ground plane. On the basis of experimental results and discussion, we conclude that a commercially available high-R wafer with carefully designed back-end process is sufficient for obtaining the maximum effect of high-R substrates.

A Low Power Multiplier Using Adiabatic Charging Binary Decision Diagram Circuit

An adiabatic charging binary decision diagram circuit (AC-BDD) is proposed that uses pass transistor logic based on a BDD and is operated by four power clocks. The AC-BDD circuit has the characteristics of a gate-level pipeline. Also proposed is a simplified switched capacitor regenerator that operates stably at any time even if the load capacitance changes variously. An 8×8 bit multiplier was designed using 0.25-µm CMOS/SIMOX (Complementary MOS/Separation by IMplanted OXygen) technology to confirm charging recovery. We found that the multiplier operates at 0.2 V and 1 MHz and its power consumption can be decreased to less than 10% that of CMOS logic.

Adaptive-Vth CMOS/SOI DC-DC Converter Scheme for 0.3-V Operation

An adaptive-Vth CMOS/SOI DC-DC converter scheme, which consists of a low-Vth charge-pump circuit and a high-Vth DC-DC converter, and enables to operate at 0.3-V, is proposed. The low-Vth circuit starts to boost a small input voltage and generates output power. And then the high-Vth converter continues the boosting operation by using the power of the low-Vth circuit. If once the high-Vth converter starts, the low-Vth circuit automatically stops the boosting operation. We fabricated the adaptive-Vth DC-DC converter with a 0.8-mum FD-SOI process and verified the converter has a conversion efficiency of more than 80% at an input voltage of 0.3 V

A sub-1V dual-threshold domino circuit using product-of-sum logic

A sub-1 V dual-threshold domino circuit is proposed to accelerate the operation of CMOS digital circuits at below 1 V. The circuit combines a low and high threshold-voltage (Vt) MOSFET with standby control to make it possible to achieve high-speed evaluation and low standby leakage current. A low-Vt foot nMOSFET is used to shorten precharge time and increase throughput. A product-of-sum logic form is used for implementation of a pull-down logic to increase the noise margin. An experimental 64-bit carry look-ahead (CLA) adder demonstrated a 0.6 V operation with a standby power of 0.4 /spl mu/W and a delay time of 4.8 ns.

Ultra-low-voltage MTCMOS/SIMOX technology hardened to temperature variation

Abstract A novel multi-threshold CMOS (MTCMOS) circuit which offers the advantage of less variation in leakage current and delay time over a wide temperature range is described. It is shown that MTCMOS/SIMOX technology, which uses a SIMOX device and combines fully depleted low-threshold MOSFETs and partially depleted high-threshold MOSFETs, can reduce variation of circuit performance due to changes in the operating temperature. To evaluate the variation in circuit performance, models of the leakage-current and the delay-time including operating temperature are derived. Calculations using the models verify that the MTCMOS/SIMOX device with threshold voltages immune to temperature changes reduces the variation. This is also confirmed by an evaluation of a gate-chain TEG designed and fabricated with 0.25 μm MTCMOS/SIMOX technology.