Shinichi Hatakeyama

Advances and Challenges in Dual-Tone Development Process Optimization

The ever-shrinking circuit device dimensions challenge lithographers to explore viable patterning for the 32 nm halfpitch node and beyond. Significant improvements in immersion lithography have allowed extension of optical lithography down to 45 nm node and likely into early 32 nm node development. In the absence of single-exposure patterning solutions, double patterning techniques are likely to extend immersion lithography for 32 nm node manufacturing. While several double patterning techniques have been proposed as viable manufacturing solutions, cost, along with technical capability, will dictate which candidate is adopted by the industry. Dual-tone development (DTD) has been proposed as a potential cost-effective double patterning technique.1 Dual-tone development was reported as early as in the late 1990s by Asano.2 The basic principle of dual-tone imaging involves processing exposed resist latent images in both positive tone (aqueous base) and negative tone (organic solvent) developers. Conceptually, DTD has attractive cost benefits since it enables pitch doubling without the need for multiple etch steps of patterned resist layers. While the concept for DTD technique is simple to understand, there are many challenges that must be overcome and understood in order to make it a manufacturing solution. This work presents recent advances and challenges associated with DTD. Experimental results in conjunction with simulations are used to understand and advance learning for DTD. Experimental results suggest that clever processing on the wafer track can be used to enable DTD beyond 45 nm half-pitch dimensions for a given resist process. Recent experimental results also show that DTD is capable of printing <0.25 k1-factor features with an ArF immersion scanner. Simulation results showing co-optimization of process variables, illumination conditions, and mask properties are presented.

LWR reduction by novel lithographic and etch techniques

The reduction of line width roughness (LWR) is a critical issue in developing resist materials for EUV lithography and LWR represents a trade-off between sensitivity and resolution. Additional post pattern processing is expected as an LWR reduction technique without impact to resolution or sensitivity. This paper reports the LWR reducing effect of a post-development resist-smoothing process. Approximately 20% improvement in LWR for ArF immersion exposed resist patterns was achieved for two types of resist and two illumination conditions. The LWR after BARC etching in which resist-smoothing was applied was decreased relative to the case in which smoothing was not applied. Resist-smoothing process also reduced LWR of an EUV exposure resist pattern by approximately 10%. These results confirm that resistsmoothing process is robust for different resists and illumination conditions.

193nm immersion process defect generation and reduction mechanism investigation using analytical methods

Utilizing de-ionized water as the medium between the wafer and lens of the exposure system and realizing high numerical aperture (NA), 193-nm immersion lithography is being developed at a great pace towards practical application. Recent improvements in materials, processing and exposure systems have dramatically reduced the defectivity levels in immersion processing. However, in order to completely eradicate immersion related defects and achieve defectivity levels required for ideal productivity, further investigation into the defect generation mechanism and full understanding of the improvements garnered so far is required. It is known that leaching of resist component materials during exposure and penetration of remaining water from the immersion scanning process are two key contributors towards immersion related defects. Additionally, the necessity to increase the hydrophobicity of the resist materials has had a signification effect on remaining resist residues. In order to more fully understand the generation of defects from the these contributions, it is necessary not only to analyze properties of the defects, but also investigate the change in composition originating from advanced processing techniques that have shown improvements in defectivity performance.

Defectivity reduction by optimization of 193-nm immersion lithography using an interfaced exposure-track system

As the integration of semiconductor devices continues, pattern sizes required in lithography get smaller and smaller. To achieve even more scaling down of these patterns without changing the basic infrastructure technology of current cutting-edge 193-nm lithography, 193-nm immersion lithography is being viewed as a powerful technique that can accommodate next-generation mass productions needs. Therefore this technology has been seriously considered and after proof of concept it is currently entering the stage of practical application. In the case of 193-nm immersion lithography, however, because liquid fills the area between the projection optics and the silicon wafer, several causes of concern have been raised - namely, diffusion of moisture into the resist film due to direct resist-water interaction during exposure, dissolution of internal components of the resist into the de-ionized water, and the influence of residual moisture generated during exposure on post-exposure processing. To prevent these unwanted effects, optimization of the three main components of the lithography system: materials, track and scanner, is required. For the materials, 193nm resist formulation improvements specifically for immersion processing have reduced the leaching and the sensitivity to water related defects, further benefits can be seen by the application of protective top coat materials. For the track component, optimization of the processing conditions and immersion specific modules are proven to advance the progress made by the material suppliers. Finally, by optimizing conditions on the 3rd generation immersion scanner with the latest hardware configuration, defectivity levels comparable to dry processing can be achieved. In this evaluation, we detail the improvements that can be realized with new immersion specific track rinse modules and formulate a hypothesis for the improvements seen with the rinsing process. Additionally, we show the current status of water induced immersion specific defect reduction using the latest advances in technology.

A CDU comparison of double patterning process options using Monte Carlo simulation

Determination of the optimal double patterning scheme depends on cost, integration complexity, and performance. This paper will compare the overall CDU performance of litho-etch-litho-etch (LELE) versus a spacer approach. The authors use Monte Carlo simulation as a way to rigorously account for the effect of each contributor to the overall CD variation of the double patterning process. Monte Carlo simulation has been applied to determine CD variations in previous studies1-2, but this paper will extend the methodology into double patterning using a calibrated resist model with topography.

Process manufacturability evaluation for next generation immersion technology node

In order to prepare for the next generation technology manufacturing, ASML and TEL are investigating the process manufacturability performance of the CLEAN TRACKTM LITHIUS ProTM-i/ TWINSCANTM XT:1900Gi lithocluster at the 45nm node. Previous work from this collaboration showed the feasibility of 45nm processing using the LITHIUSTM i+/TWINSCAN XT:1700i. 1 In this work, process performance with regards to critical dimension uniformity and defectivity are investigated to determine the robustness for manufacturing of the litho cluster. Specifically, at the spinner and PEB plate configuration necessary for the high volume manufacturing requirement of 180 wafers per hour, process data is evaluated to confirm the multi-module flows can achieve the required process performance. Additionally, an improvement in the edge cut strategy necessary to maximize the usable wafer surface without negative impact to defectivity is investigated.

Image Contrast Contributions to Immersion Lithography Defect Formation and Process Yield

As the industry extends immersion lithography to the 32 nm node, the limits of image and resist contrast will be challenged. Image contrast is limited by the inherent numerical aperture of a water based immersion lithography system. Elements of resist design and processing can further degrade the final deprotected image contrast1,2. Studies have been done to understand the effects of image contrast on line width roughness (LER) for dry 193 nm lithography3. This paper focuses on the impacts of image and resist contrast on the formation of defects and LER in an immersion lithography process. Optical and resist simulations are combined with experiments to better understand the relationship between image quality, resist design, scanner/track processing and defect formation. The goal of this work is to develop a relationship between resist contrast metrics and defect formation for immersion processes.

Initial process evaluation for next generation immersion technology node

In order to prepare for the next generation technology manufacturing, ASML and TEL are working together to investigate the process performance of the LITHIUSi+/ TWINSCAN XT:1700i lithocluster through decreasing critical dimension patterning. In this evaluation, process performance with regards to critical dimension uniformity and defectivity are compared at different critical dimensions in order to determine areas of concentration for equipment and process development. Specifically, design of experiments were run using immersion rinse processing at 60nm hp and 45nm hp. Defects were classified to generate a pareto for each technology node to see if there is any change in the defect types as critical dimensions are shrinking. Similarly, critical dimension uniformity was compared through technology nodes to see if any budget contributions have increased sensitivities to the smaller patterning features. Preliminary gauge studies were performed for the 45nm hp evaluation, as metrology at this design rule is not yet fully proven. More work is necessary to obtain complete understanding of metrology capabilities as this is crucial to discern precise knowledge of processing results. While preliminary results show no adverse impact moving forward, this work is a first screening of 45nm immersion processing and more work is needed to fully characterize and optimize the process to enable robust manufacturing at 45nm hp.