Shinichi Murai

Test Generation for Scan Design Circuits with Tri-State Modules and Bidirectional Terminals

This paper describes a program which generates test patterns for scan design circuits with tri-state modules and bidirectional terminals. The test generation procedure uses a path sensitization technique with 14 signal values. The principal features of this program are test generation with automatic decision of I/O mode of bidirectional terminals, generation of test sets for high impedance state, and generation of test sets for system clock control circuits of shift register latches (SRLs) by using shift-in function of SRLs.

A Hierarchical Placement Procedure with a Simple Blocking Scheme

The outline of a hierarchical placement procedure utilizing a simple blocking scheme is described with the results of the application to the DSA-MOS gate arrays. Indirect clustering value is introduced for the blocking, i.e. grouping of modules under block size restriction. The system including the procedure has been successfully applied to the design of MOS gate arrays with effectively no manual assistance.

LORES-2: A Logic Reorganization System

LORES-2 is a logic reorganization system which greatly contributes to the effective automation of logic design. LORES-2 uses a macro-expansion technique to help designers transform printed-circuit assembly logic composed of SSI and MSI circuits into master-slice LSI logic circuits. The number of gates of the most reorganized LSI circuit falls within ± 20 percent of the number of gates of the original circuit. When ROMS and/or PLAs are not-allowed on the target LSI circuit, those elements are converted into optimized, multilevel random logic using logic minimization, factoring and macro-expansion techniques.

Tri-state bus conflict checking method for ATPG using BDD

This paper describes a bus design rule checking method which efficiently checks whether signal conflicts may occur on the tri-state buses in a given circuit and whether the buses may be in floating states. By using BDD (binary decision diagram) representations, a practical bus design rule check program has been obtained.

An Integrated Computer Aided Design System for Gate Array Masterslices: Part 1. Logic Reorganization System Lores-2

The outline and the application results of a computer aided logic design system which combines automatic translation of TTL SSI/MSI logic into gate array logic, human intervention, auxiliary logic simulation, and automatic documentation are described. Automaic translation of logic circuit is done by macro expansion technique coupled with redundant logic reduction procedures.

ASTA: LSI Design Management System

This paper deals with an LSI design management system which automates CAD program performance analysis. CAD program/library version control, design process control, design cost estimation and the collection of such statistical information as the sizes of the circuits being designed. The design management automation has been accomplished by analyzing statistical and control information generated by all the CAD programs and the operating system.

A skew assumption logic simulation technique for potential spike detection

A simulation technique that a set of signal transitions which may cause the simulated circuit to exhibit incorrect behavior by assuming event skew is described. Incorporation of timing check primitive enables detailed timing error messages composed of the past signal transitions at the primary inputs which cause the error, the internal gate which generates the potential spike signal and the internal signal transitions related to the error. The logic simulator on which the novel simulation technique is installed helps designers to find hazardous designs in the circuit under verification. LSIs verified by using the simulator are free from timing skew troubles on the bench of ATE (Automatic Test Equipment).<<ETX>>

MULTES/IS: An Effective and Reliable Test Generation System for Partial Scan and Non-Scan Synchronous Circuits

This paper describes an automatic test generation system which effectively generates test vectors by recognizing the circuit blocks for which vectors are automatically generated and the circuit blocks for which vectors have to be manually prepared. Test vectors for full scan, partial scan and non-scan synchronous circuit blocks are automatically generated. Test vectors for asynchronous circuit blocks have to be manually prepared.

PATEGE: An Automatic DC Parametric Test Generation System for Series Gated ECL Circuits

For ECL circuits. DC parametric tests such as input current (IIL IIH), reference voltage (VBB), and power supply current (ICC) tests are executed as well as functional tests. This paper describes: an automatic DC parametric test generation system PATEGE for the series gated ECL circuits. PATEGE can automatically generate the test patterns and calculate the expected values for IIL, IIH, VBB and ICC tests.