H. Toyoshima

A 16 Mb 400 MHz loadless CMOS four-transistor SRAM macro

0.18 /spl mu/m logic process technologies have recently been used to develop a loadless CMOS four-transistor SRAM cell (4T-cell) whose size (1.934 /spl mu/m/sup 2/) is only 56% that of a conventional six-transistor SRAM cell (6T-cell). Using this 4T-cell technology. The authors present a 16 Mb, 400 MHz SRAM macro which features: (1) an end-point dual-pulse driver (EDD) for stable data hold and minimum cycle time, (2) word-line-voltage-level compensation (WLC) for stable static data hold, and (3) an all-adjoining twist bit-line (ATBL) to reduce bit-line coupling capacitance.

In surface segregation and growth‐mode transition during InGaAs growth by molecular‐beam epitaxy

An In surface segregation effect during the growth of InGaAs on GaAs by molecular‐beam epitaxy has been studied by reflection high‐energy electron diffraction measurements supported by a segregation model. Indium atoms segregate at a ratio of more than 0.8 under the conventional growth conditions for InGaAs, which causes the formation of accumulated In atoms on the surface. The transition from two‐dimensional to three‐dimensional growth occurs when the amount of In reaches around 1.7 monolayer with a nominal alloy composition greater than 0.25. This transition determines the upper limit on the In composition of the InGaAs layer for application as an electron channel in modulation‐doped field‐effect transistors.

NV-SRAM: a nonvolatile SRAM with backup ferroelectric capacitors

This paper demonstrates new circuit technologies that enable a 0.25-/spl mu/m ASIC SRAM macro to be nonvolatile with only a 17% cell-area overhead. New capacitor-on-metal/via-stacked-plug process technologies permit a nonvolatile SRAM (NV-SRAM) cell to consist of a six-transistor ASIC SRAM cell and two backup ferroelectric capacitors stacked over the SRAM portion. READ and WRITE operations in this NV-SRAM cell are very similar to those of a standard SRAM, and this NV-SRAM shares almost all the circuit properties of a standard SRAM. Because each memory cell can perform STORE and RECALL individually, both can execute massive-parallel operations. A V/sub dd//2 plate-line architecture makes READ/WRITE fatigue negligible. A 512-byte test chip was successfully fabricated to show compatibility with ASIC technologies.

A new low-noise AlGaAs/GaAs 2DEG FET with a surface undoped layer

A high-performance N-AlGaAs/GaAs selectively doped two-dimensional electron gas (2DEG) FET with a surface undoped layer has been designed and demonstrated. Simple analysis based on the short-channel approximation revealed that an increase in a total layer thickness between a gate electrode and 2DEG at a hetero-interface results in a higher cutoff frequency and a lower noise figure than conventional 2DEG FETs. This is because the gate capacitance can be markedly reduced without a significant decrease in the transconductance owing to a parasitic source resistance. The surface undoped layer intentionally employed in this work can permit the total layer thickness to increase, i.e., the gate capacitance to reduce, without changes in the 2DEG density and in the source resistance. This structure also gives high gate breakdown voltage because of a small neutral region in n- (AlGa)As and a low surface electron field, which possibly yields excellent performance 2DEG FETs for practical use. Fabricated (AlGa)As/ GaAs 2DEG FETs exhibited noticeable room-temperature performances of 0.95-dB noise figure with 10.3-dB associated gain at 12- and 45-GHz cutoff frequency. These are the best data ever reported for 0.5-µm gate length FETs.

Growth by molecular‐beam epitaxy and characterization of (InAs)m(GaAs)m short period superlattices on InP substrates

(InAs)m(GaAs)m short period superlattices (SPSs) have been grown by molecular‐beam epitaxy on InP substrates with their layer index m value systematically changed from 1 to 3. Their structural and electrical property dependencies on the layer index m value have been examined. During the first growth stage for the SPSs, with layer index m values of 2 and 3, two‐dimensional reflection high‐electron energy diffraction growth patterns were observed. The intended periodic structures without misfit dislocation generation were confirmed by x‐ray diffraction and transmission electron microscopy (TEM) measurements. However, the obtained electrical properties were still poor, indicating the existence of a large amount of disorder in the SPSs. On the other hand, though the thickness of consisting binary compounds was as thin as one monolayer, a high‐quality (InAs)1(GaAs)1 SPS was obtained. The highly ordered monolayer arrangement for InAs and GaAs was first observed by a TEM lattice image as well as x‐ray diffractio...

A 500 MHz 4 Mb CMOS pipeline-burst cache SRAM with point-to-point noise reduction coding I/O

A secondary cache SRAM is an indispensable CPU partner in a high-performance system. The main objectives are: 1) pipeline burst operation; 2) 32b 500MHz (2GB/s) I/Os, and 3) point-to-point communication with a CPU, as well as shortened latency and reduced noise and power caused by high-speed, high-bandwidth I/O operation. A pre-fetched pipeline scheme enables the cycle time for an internal memory core (I-cycle) to be extended by N times that of an external bus cycle (E-cycle). This is modified to an SRAM to achieve both 4b pipeline-burst cache operation and 500MHz I/O frequency. In this case, I-cycle time of 8ns is four times E-cycle time (2ns).

The design, fabrication, and characterization of a novel electrode structure self-aligned HBT with a cutoff frequency of 45 GHz

This paper establishes a systematic approach for the design, fabrication, and modeling of a newly proposed self, aligned Al-GaAs/GaAs heterojunction bipolar transistor (HBT) employing a two-dimensional heterostructure device simulator and a heterojunction bi-polar transistor circuit simulator. The developed HBT has an abrupt emitter-base heterojunction, and applies a novel structure in which a single base electrode is placed between two emitter electrodes. A fabricated 3 × 8 µm2two-emitter HBT exhibits a measured current gain cutoff frequency fT= 45 GHz and a maximum oscillation frequency fmax= 18.5 GHz. Results of frequency divider circuit Simulation indicate that the developed HBT would be 1.4 times faster than a conventional HBT in which one emitter electrode is located between two base electrodes.

An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield

We have developed two schemes for improving access speed and reliability of a loadless four-transistor (LL4T) SRAM cell: a dual-layered twisted bitline scheme, which reduces coupling capacitance between adjacent bitlines in order to achieve highspeed READ/WRITE operations, and a triple-well shield, which protects the memory cell from substrate noise and alpha particles. We incorporated these schemes in a high-performance 0.18-/spl mu/m-generation CMOS technology and fabricated a 16-Mb SRAM macro with a 2.18-/spl mu/m/sup 2/ memory cell. The macro size of the LL4T-SRAM is 56 mm/sup 2/, which is 30% to 40% smaller than a conventional six-transistor SRAM when compared with the same access speed. The developed macro functions at 500 MHz and has an access time of 2.0 ns. The standby current has been reduced to 25 /spl mu/A/Mb with a low-leakage nMOSFET in the memory cell.

A high transconductance GaAs MESFET with reduced short channel effect characteristics

A high gm, 375 mS/mm (Vth= -0.09 V), has been achieved from a 0.3 µm long gate GaAs MESFET with a very small short channel effect by employing an MBE grown channel layer. The maximum K - value obtained was 410 mS/Vmm, which is the highest ever reported for GaAs MESFETs. A unique technology, combining sidewall - assisted self - alignment technology (SWAT) and refractory metal gate n+selective ion - implantation technology, was successfully applied to the fabrication of a GaAs MESFET with MBE grown channel layer in this work, resulting in a very low source series resistance of 0.3 Ωmm. FET characteristic dependences on gate length were also compared for FETs with different doping concentrations. The highly doped channel turned out to be effective to reduce the short channel effects and to improve the FET load drivability.

Molecular‐beam epitaxial growth of InAs/GaAs superlattices on GaAs substrates and its application to a superlattice channel modulation‐doped field‐effect transistor

The molecular‐beam epitaxial growth conditions for (InAs)m(GaAs)n short period superlattices (SPSs) on GaAs substrates have been optimized by monitoring reflection high‐energy electron diffraction (RHEED) intensity oscillations. The RHEED oscillation measurements enable understanding InAs growth behavior on a 7% lattice‐mismatch GaAs substrate. Within one monolayer InAs deposition with lower than 560 °C growth temperature can give high SPS crystalline quality. The SPS periodic structure and the monolayer InAs formation, embedded in GaAs layers, have been confirmed by x‐ray diffraction and transmission electron microscopy measurements. The obtained thickness controllability for the SPSs is less than±6% for InAs and ±3% for GaAs. The electron Hall mobilities for modulation‐doped structures having an (InAs)1(GaAs)n SPS as an electron channel, whose layer index of n varied from 3 to 6, have been compared with those with a pseudomorphic InGaAs random alloy channel which has the equivalent In composition. The S...