Shunichiro Nakamura

LORES - Logic Reorganization System

Described is the outline and the experimental results of the system which automatically restructures and partitions a logic circuit consisting of standard SSIs and MSIs so that the gate types and the numbers of input/output terminals of the reorganized circuits are within the restrictions of the specified LSI.

A High Speed Database Machine HDM

To meet the increasing demand for the speedup of relational database processing, we are developing a prototype of HDM (it stands for a High Speed Database Machine). HDM is a relational database machine which has a simple structure with five 32-bit microprocessors, Motorola’s MC 68020s. HDM can execute relational database processing very fast by the parallel processing and the best suited disk access method etc. The subset of SQL which includes almost all the basic functions is implemented on the HDM. It is still being developed, but the performance evaluation about selection, projection and join queries without indices has proved that HDM can execute these queries fairly faster than some other relational database systems. In this paper, we present the hardware and software design of HDM and the results of the performance evaluation.

LORES-2: A Logic Reorganization System

LORES-2 is a logic reorganization system which greatly contributes to the effective automation of logic design. LORES-2 uses a macro-expansion technique to help designers transform printed-circuit assembly logic composed of SSI and MSI circuits into master-slice LSI logic circuits. The number of gates of the most reorganized LSI circuit falls within ± 20 percent of the number of gates of the original circuit. When ROMS and/or PLAs are not-allowed on the target LSI circuit, those elements are converted into optimized, multilevel random logic using logic minimization, factoring and macro-expansion techniques.

An Integrated Computer Aided Design System for Gate Array Masterslices: Part 1. Logic Reorganization System Lores-2

The outline and the application results of a computer aided logic design system which combines automatic translation of TTL SSI/MSI logic into gate array logic, human intervention, auxiliary logic simulation, and automatic documentation are described. Automaic translation of logic circuit is done by macro expansion technique coupled with redundant logic reduction procedures.

A High Speed Database Machine HDM and its Performance Evaluation

To meet the increasing demand for speeding up relational database processing, we developed a database machine HDM and presented it at the 5th IWDM in 1987. Here, we present the results of a performance evaluation of HDM by ‘Wisconsin Benchmark’ and ‘Expanded Wisconsin Benchmark.’ The results of the evaluation show that HDM can execute various relational database operations fairly faster than some other database systems or database machines.