Shinpei Hijiya

Analysis of p/sup +/ poly Si double-gate thin-film SOI MOSFETs

The authors have fabricated planar p/sup +/ poly Si double-gate thin-film SOI (silicon-on-insulator) nMOSFETs using wafer bonding. The fabricated devices have shown a transconductance, Gm, exceeding twice that of the single-gate SOI-MOSFET. It was confirmed that conduction in the double-gate SOI MOSFET originates from a fully flat potential and charge injection. An analytical model developed by the authors has displayed electrical characteristics that agree well with those of the fabricated devices.<<ETX>>

A wafer-scale 170000-gate FFT processor with built-in test circuits

The wafer-scale 170000-gate fast Fourier transform (FFT) processor described consists of individual repeatable building blocks, each of which contains a processing element (PE) and interconnection wiring. The PE consists of a multiplier accumulator and its built-in self-test circuits. The wafer system is reconfigured by connected active blocks after block self-diagnosis. Blocks are connected using a programmable contact-hole mask. The processor performs parallel 16-bit, eight-point complex FFTs and is implemented with 725 I/O pads in triple-metal 2.3- mu m p-well CMOS technology on a 4-in. wafer. It is mounted by controlled-collapse bonding facedown on a 11.8*11.8-cm/sup 2/ substrate. >

Study on Chlorine Adsorbed Silicon Surface Using Soft-X-Ray Photoemission Spectroscopy

In a study of the surface reaction of molecular and atomic chlorine on Si(100) and Si(111) using X-ray photoemission spectroscopy and molecular beam scattering, we have found only SiCl in the chlorinated layer formed by the molecular chlorine exposure, with no change in this bonding configuration after annealing. Most desorption products were SiCl2. SiCl desorbed above 900°C, probably due to the recombinative desorption of SiCl+Cl→SiCl2. SiCl desorbed directly from the surface without any reaction. Heavily chlorinated species, such as SiCl2, SiCl3 and SiCl4, were observed on Si(100) and Si(111) surfaces exposed to atomic chlorine. These heavily chlorinated species quickly desorbed from the surface after annealing at 300°C. No heavily chlorinated species were observed on the silicon surface exposed to molecular chlorine. The chlorinated layer on Si(111) was thinner than that on Si(100), explaining the appearance of the facet reported in photo-enhanced etching.

Chlorine molecular beam scattering study on Si(100)2 × 1: desorption products

Abstract We have studied the surface reaction of chlorme on silicon, using molecular beam reactive scattering. We have investigated the desorption products from a Si(100)2 × 1 surface with chlorine molecular beam irradiation, and measured the ionization efficiency of SiCl to identify the desorption products. Below 600°C, scattered chlorine molecules were observed. Chlorine adsorbed on the Si(100)2 × 1 surface and desorption of the chloride species was not detected. Above 600°C, desorption of chloride from the surface was observed. Most of the desorption products were dichlorides and monochloride desorbed slightly from the surface. The reaction probability of chlorine is almost 100°C above 600°C. Above 800°C, monochloride desorbed directly and the amount of the desorbed monochloride increased with sample temperature. The energies at which SiCl * appeared from monochloride and dichlorides were 6.8 and 11.5 eV, respectively.

1.5 &#181;m Gate CMOS operated at 77 K

The advantages of CMOS operation at the liquid nitrogen temperature (77 K) and limitations caused by hot-carrier effects are examined. In particular, the continuous temperature dependence of CMOS devices from 300 K to 77 K has been measured for the first time. There are gate length dependence and gate field dependence in the change of each transistors transconductance from at 300 K to at 77 K. The saturation of carrier velocity is considered to be a reason for these phenomena.

A wafer-scale FFT processor featuring a repeatable building block

The wafer-scale 170000-gate fast Fourier transform (FFT) processor has three features: a single repeatable building block containing a processing element (PE) and its interconnects, mask-programmable routing by the placement of contact holes, and a built-in self-test (BIST) for the PE and its interconnects. The wafer system is composed of 48 PEs selected out of a total of 88 PEs. The PE consists of a 2800-gate multiplier-accumulator and 700-gate BIST circuitry. The processor performs parallel 16-bit, 8-point complex FFT and is implemented with 725 I/O pads in triple-metal 2.3- mu m CMOS technology on a 4-inch wafer. This wafer is mounted face down on an 11.8*11.8-cm/sup 2/ substrate by solder bumps.<<ETX>>

Electrically alterable read-only memory cell with graded energy band-gap insulator

Low voltage alterability and excellent memory retention have been obtained with a novel EAROM cell that has a graded energy band-gap film as the first insulator of a Floating-Gate type memory. The graded energy band-gap insulator can enhance charge injection without deteriorating memory retention, because the energy band-gap is narrowed only at the silicon substrate interface. A graded energy band-gap insulator has been realized by thermally oxidizing the surface of a very thin silicon nitride film grown by direct thermal nitridation of a silicon substrate. A fabricated EAROM cell has shown that it can be programmed by a single positive supply of less than 12 V and it has excellent memory retention.

p/sup +/ polysilicon gate P-MOSFETs using BCl implantation

Suppressing boron penetration through the gate oxide is necessary to give reliable p/sup +/ polysilicon gate P-MOSFETs which are expected to ease the short channel effect. Fluorine was automatically introduced in the gate oxide by BF/sub 2/ implantation and enhanced B diffusion. It is clearly demonstrated that chlorine does not enhance B diffusion. BCl implantation when fabricating p/sup +/ polysilicon gates makes it possible to fabricate quarter-micron gate length P-MOSFETs with pure oxide 4.5 nm thick.<<ETX>>

A nitride-barrier avalanche-injection EAROM

A 10 nm graded band-gap insulator obtained by oxidizing the surface of a very thin thermal nitride film has been used as the first insulator of a floating gate avalanche-injection EAROM cell. A low-energy barrier of thermal nitride and a cell optimization considering the capacitive coupling of the floating gate to the drain has enabled low single-polar voltage alterability on a 2 kbit test vehicle. Good write/erase endurance has been also obtained owing to the low injection field applied to the first insulator of the avalanche injection approach.

Test Methods for Wafer-Scale Integration

Wafer-scale integration (WSI) is expected to yield higher speed and better reliability and to drastically improve circuit density. The essential problem is that WSI cannot be fabricated without defects because the number of defects increases with circuit area. WSI systems require redundant silicon areas to enhance yield, and must be reconfigured by detecting faulty parts and substituting them with spares. It is important to obtain adequate yield by decreasing the redundant area as much as possible.