Shinsaku Saito

A 60-ns 1-Mb nonvolatile ferroelectric memory with a nondriven cell plate line write/read scheme

With increase in the capacity of nonvolatile memories, the range of their use has been widening. A nonvolatile ferroelectric RAM (NVFRAM) based on a 1-transistor and 1-capacitor (1T/1C) memory cell has potential for fast-access time and small-chip size comparable with a DRAM. However, previously reported NVFRAMs are still slower than ordinary DRAMs, since driving a cell-plate line in NVFRAMs is slow. To avoid this, a non-driven cell plate line write/read scheme (NDP scheme) is presented which leads to NVFRAMs with as fast access time as DRAMs.

A 90nm 12ns 32Mb 2T1MTJ MRAM

Since MRAM cells have unlimited write endurance, they can be used as substitutes for DRAMs or SRAMs. MRAMs in electronic appliances enhance their convenience and energy efficiency because data in MRAMs are nonvolatile and retained even in the power-off state. Therefore, 2 to 16Mb standalone MRAMs have been developed [1–4]. However, in terms of their random-access times, they are not enough fast (25ns) [1] as substitutes for all kinds of stand-alone DRAMs or SRAMs. To attain a standalone MRAM with both a fast random-access time and a large capacity, we adopt a cell structure with 2 transistors and 1 magnetic tunneling junction (2T1MTJ), which we previously published for a 1Mb embedded MRAM macro [5]. We need to develop circuit schemes to achieve a larger memory capacity and a higher cell-occupation ratio with small access-time degradation. We describe the circuit schemes of a 32Mb MRAM, which enable 63% cell occupation ratio and 12ns access time.

MRAM Cell Technology for Over 500-MHz SoC

This paper describes newly developed magnetic random access memory (MRAM) cell technology suitable for high-speed memory macros embedded in next-generation system LSIs: a two-transistor one-magnetic tunneling junction (2T1MTJ) cell structure, a write-line-inserted MTJ, and a 5T2MTJ cell structure. The 2T1MTJ cell structure makes it possible to significantly improve the write margin and accelerate the operating speed to 200 MHz. Its high compatibility with SRAM specifications and its wide write margin were confirmed by measuring 2T1MTJ MRAM test chips. Although the cell structure requires a small-writing-current MTJ, the current can be reduced to 1mA using the newly developed write-line-inserted MTJ. Further development to reduce the current down to 0.5 mA is required to obtain a cell area of 1.9 mum2, which is smaller than the SRAM cell area, in the 0.13-mum CMOS process. The 5T2MTJ cell structure also enables random-access operation over 500 MHz because the sensing signal is amplified in each cell. Random access time of less than 2 ns can be achieved with SPICE simulation when the magnetic resistance is 5 kOmega and the magnetoresistive (MR) ratio is more than 70%

Miniaturized thin-film magnetic field probe with high spatial resolution for LSI chip measurement

It is important to obtain the absolute value of current flowing through each power line on a large-scale integrated (LSI) circuit by measurement because this current on an LSI chip is regarded as conductive noise. We have developed a thin-film magnetic field probe that has spatial resolution high enough to obtain the absolute value of high-frequency power current on an LSI chip. Spatial resolution was enhanced by miniaturizing the shielded loop coil, the detection part of the probe. The outer size of the new coil is 50/spl times/22 /spl mu/m. In taking measurements with the new probe over a 60 /spl mu/m wide microstrip line used as a device under test (DUT), we obtained a 6 dB decrease point of 40 /spl mu/m, which indicates the spatial resolution of the probe. This value is comparable to the typical width of power lines on an LSI chip, around 50 /spl mu/m and is less than half that of our conventional probes, around 90 /spl mu/m. In measurements with the new probe over an LSI chip, we obtained such a fine magnetic near-field distribution that the magnetic fields generated from the lines on the chip were separated. On-chip decoupling was also confirmed by using the new probe. The new probe enables direct verification of a circuit design for suppressing electromagnetic interference (EMI), while conventional coarse mapping of the magnetic near-field cannot be used to evaluate such conductive noise.

Improvement of Thermal Stability of Magnetoresistive Random Access Memory Device with SiN Protective Film Deposited by High-Density Plasma Chemical Vapor Deposition

Embedded magnetoresistive random access memory (MRAM) with multi-level interconnects necessitates that magnetic tunnel junction (MTJ) devices have a thermal stability of 350 °C or higher during fabrication. We have improved thermal stability of MRAM devices using SiN protective film deposited by high-density plasma chemical vapor deposition (HDP-CVD) at 200 °C. The MTJ devices with HDP-CVD SiN protective film did not degrade after post-annealing at 350 °C, which suggests that the HDP-CVD process reduced oxide metal on the etched surface of the MTJ devices and that the SiN film blocked H2O diffusion from the interlayer dielectric film during post-annealing at 350 °C. We also fabricated a 1-kbit MRAM array and experimentally demonstrated thermal stability at 350 °C.

MRAM Cell Technology for Over 500MHz SoC

We propose two new MRAM cell structures, 2T1MTJ and 5T2MTJ. Although they enable very high-speed operation, they require small-write-current magnetic tunnel junctions (MTJs). We found that write current could be reduced to 1mA by a novel MTJ into which a write line is inserted. The 5T2MTJ cell has two write current switches and a sense circuit. Simulation results show that access time of under 1ns is achieved when the magnetic resistance is 5k-ohm and its ratio (MR) is 150%

A 250-MHz 1-Mbit embedded MRAM macro using 2T1MTJ cell with bitline separation and half-pitch shift architecture

A 250-MHz 1-Mbit MRAM macro is demonstrated in a 0.15-mum standard CMOS process with 1.5-V supply. Its clock frequency is the highest among the MRAMs that have been reported. It has a highly compatible embedded-SRAM interface. The macro is designed using a 6.97-mum2 bitline separated and half-pitch shifted 2-transistor 1-magnetic tunnel junction (2T1MTJ) cell. The half-pitch-shift arrangement enables efficient reduction of bitline capacitance and a symmetrical reading scheme, which accelerates the random access clock frequency to the same speed as that of SRAMs. The technology will help to achieve MRAM embedded systems on chips (SoCs).

A 16-Mb Toggle MRAM With Burst Modes

This paper describes a recently developed 16-Mb toggle magnetic random access memory (MRAM). It has 100-MHz burst modes that are compatible with a pseudo-SRAM even though the toggle cell requires reading and comparing sequences in write modes. To accelerate operating clock frequency, we propose a distributed-driver wide-swing current-mirror scheme, an interleaved and pipelined memory-array group activation scheme, and a noise-insulation switch scheme. These circuit schemes compensate the toggle cell timing overhead in write modes and maintain write-current precision that is essential for the wide operational margin of MRAMs. Because toggle cells are very resistant to write disturbance errors, we designed the 16-Mb MRAM to include a toggle MRAM cell. The MRAM was fabricated with 0.13-mum CMOS and 0.24-mum MRAM processes with five metal layers.

Highly-Reliable Low-Resistance Cu Interconnects with PVD-Ru/Ti Barrier Metal toward Automotive LSIs

Highly-reliable Cu interconnects with Ru/Ti barrier metal have been developed, in which Ti is diffused into the Ru-layer to establish a Cu-diffusion barrier. The PVD-Ru/Ti barrier metal with preferable crystal-orientation to Cu texture achieves the low line resistance. The Ti-doping in the Cu grain boundary just under the via improves the Cu-via reliabilities, besides keeping the Cu line resistance low. The Cu line with the Ru/Ti barrier metal is a strong candidate for automotive LSIs in future, requiring high performance and ultra-high reliability.

Dual hard mask process for low-k porous organosilica dielectric in copper dual damascene interconnect fabrication

Using a low-k porous organosilisesqueoxane film, ALCAP/sup TM/-S with k=2.1, dual hard mask (DHM) process is proposed for Cu dual damascene interconnect (DDI) formation. The porous organosilica film has very high etching rate relative to those of the hard mask (HM) and/or etch-stop materials. SiO/sub 2//SiC is one of the best combinations for the DHM, in which the lower hard mask of SiC remained after metal CMP and protects the porous film from the via-etching damage in misalignnent region between the via-hole and the buried Cu-line. Applying in-situ resist-ashing with N/sub 2//H/sub 2/ gas, 0.4 /spl mu/m-pitched dual damascene structure is successfully fabricated. Increment of the dielectric constant is suppressed within 5% (k=2.2) after the Cu-interconnect fabrication, confirming that the DHM low-damage process is applicable for the Cu DDI fabrication in ultra low-k, porous organosilica systems.