Shinsuke Konaka

A 30-ps Si bipolar IC using super self-aligned process technology

A new 30-ps Si bipolar IC technology has been developed by scaling down a bipolar transistors lateral geometry and forming shallow junctions. The n-p-n transistor has a 0.35-µm-wide emitter and a 1.57-µm-wide base region fabricated using super self-aligned process technology (SST) with 1-µm rule optical lithography. The fTvalues achieved for this device are 13.7 GHz at a collector-emitter voltage of 1 V and 17.1 GHz at 3 V. Propagation delay times (fan-in = fan-out = 1) of 30 ps/gate at 1.48 mW/gate for nonthreshold logic and 50 ps/ gate at 1.46 mW/gate for low-level current mode logic have been achieved.

A 20-ps Si bipolar IC using advanced super self-aligned process technology with collector ion implantation

A super self-aligned process technology, SST-1B, which is an advanced version of the previously proposed SST-1A in high-speed Si bipolar LSIs is discussed. A selectively ion-implanted collector (SIC) process and birds-beak-free isolation process are utilized. The SIC process is designed to improve shallow base-collector profiles in the intrinsic region. It reduces base width and intrinsic base resistance, and suppresses the base push-out effect (Kirks effect) in high-current operations. The SIC profile is easily controlled by 150-200 keV phosphorous ion implantation at the base-collector junction. Using these processes, SST-1B has achieved a high cutoff frequency of 21.1 to 25.7 GHz and a fast switching delay of 20.5 ps/G for nonthreshold logic and 34.1 ps/G for emitter-coupled logic. SST-1B has potential applications to 50-ps/G logic LSIs and 10-GHz SSIs. Device simulation indicates that it is possible to achieve a cutoff frequency of 40-50 GHz in a future scaled-down Si bipolar transistor with a 40-nm base and graded collector. >

Si bipolar 2-GHz 6-bit flash A/D conversion LSI

A gigahertz-sampling-rate flash A/D (analog/digital)-conversion LSI using high-speed Si bipolar technology (SST-1B) is investigated. To improve comparator speed, a circuit technology to minimize the comparator-speed limiting factors with minimum power is investigated and applied. To enhance the dynamic accuracy, speed mismatch among comparators is also minimized using this circuit technology. To improve encoder speed, a quasi-Gray code is adopted and glitch noise is reduced with this code. The LSI performance at 1-GHz sampling rate is measured with a gigahertz-operation data acquisition system developed with the SST MSI family, and effective bits of 5.8 at an input frequency of 100 MHz and 4.8 at 500 MHz are achieved. This LSI also demonstrates the feasibility of a single-chip flash A/D converter with a gigahertz sampling rate using Si bipolar technology. >

Design method of MTCMOS power switch for low-voltage high-speed LSIs

The design of the power switch which turns on and off the power supply to the logic gates is essential to low-voltage high-speed circuit techniques such as multi-threshold voltage CMOS (MTCMOS). This is because this switch influences the speed, area, and power of a low-voltage LSI. This paper describes the influences of the power switch on the circuit performance in detail, and proposes a systematic method for designing a power switch which takes them into consideration for the first time. The main feature of this method, called the average-current method, is the use of the average current consumed in an LSI to determine the power-switch size. This makes it easy for designers to determine the minimum size of the power-switch needed to satisfy the required speed, which results in minimizing the area penalty and the standby power. Useful analytical formula and the practical determination flow are also described. Measurement of an actual 0.25 /spl mu/m MTCMOS/SIMOX 290-Kgate LSI operating at 1 V confirmed the effectiveness of this method. This method estimated well the required power-switch width, and as a result it reduced the area penalty and standby current by about 80% compared to the conventional design scheme.

18-GHz 1/8 dynamic frequency divider using Si bipolar technologies

Circuit technology to achieve high-speed frequency dividers using Si bipolar devices is studied. A novel circuit configuration based on regenerative frequency division was proposed and analyzed. It is determined that the 3-dB-down bandwidth of the open loop of the novel circuit configuration is three times higher than that of the conventional circuit and that it operates almost up to the f/sub T/ of the transistor. A 1/8 dynamic divider using this novel circuit configuration was fabricated with advanced super self-aligned process technology (SST-1B). The divider operates between 4.6 and 18 GHz. It is noted that the circuit technology and process technology described are applicable to very-high-speed prescalers for satellite communication systems and high-speed measuring equipment. >

A 9-GHz frequency divider using Si bipolar super self-aligned process technology

A very high-speed 1/8 frequency divider is fabricated, using Si bipolar super self-aligned process technology (SST), and tested. The circuit consists of three T-connected D-type master-slave flip-flops and buffers. A low voltage swing (225 mV) differential circuit technique is adopted for the first stage T-type flip-flop. The divider is capable of operating at up to 9 GHz with a power dissipation of 554 mW.

A new silicon‐on‐insulator structure using a silicon molecular beam epitaxial growth on porous silicon

A new silicon‐on‐insulator (SOI) structure has been achieved by utilizing silicon molecular beam epitaxial (Si‐MBE) growth on porous silicon, silicon island patterning, and the subsequent laterally enhanced oxidation of the porous silicon. The surface of Si‐MBE film grown on porous silicon at 770 °C without high‐temperature preheating has a 7×7 superlattice structure when observed by a reflection high‐energy electron diffraction (RHEED). Patterned Si‐MBE film island, that is 7.0 μm wide and 0.35 μm thick, is successfully isolated by the laterally enhanced oxidation of porous silicon.

Prospects of SST technology for high speed LSI

SST has realized very high speed integrated circuits with a basic gate delay time of 25.8 ps/gate. Also, a 10.38 GHz frequency divider, a 0.85 ns 1 Kb RAM and a 6 ns 16×16 bit parallel multiplier are fabricated using SST with 1um optical lithography. For a scaled-down SST transistor, the basic gate delay time is expected to be less than 10 ps/gate.

Bipolar monolithic amplifiers for a gigabit optical repeater

Main amplifier, AGC amplifier, and preamplifier ICs have been designed and fabricated using an advanced silicon bipolar process to provide the required characteristics of repeater circuits for a gigabit optical fiber transmission system. The bipolar technology used involved a separation width of 0.3 /spl mu/m between the emitter and the base electrode. New circuit techniques were also used. The differential type main amplifier has a peaking function which can be varied widely by means of DC voltage supplied at the outside IC terminal. A bandwidth which can be varied to about three times the value for a nonpeaking amplifier is easily obtained. The gain and maximum 3-dB down bandwidth were 4 dB and 4 GHz, respectively. The main feature of the AGC amplifier is that the diodes are connected to the emitters of the differential transistor pair to improve the linearity. The maximum gain and 3-dB down bandwidth were 15 dB and 1.4 GHz, respectively, and a dynamic range of 25 dB was obtained. The preamplifier has a shunt-series feedback configuration. Furthermore, a gain and 3-dB down bandwidth of 22 dB and 2 GHz, respectively, were achieved with an optimum circuit design. The noise figure obtained was 3.5 dB.

A low-permittivity interconnection using an SiBN interlayer

A low-permittivity two-level interconnection process is presented. The key features of this process are the use of a low dielectric constant SiBN interlayer and the adoption of planarization using a two-stage etch-back process. The SiBN film is characterized from the standpoint of its device applications. The two-level interconnection process flow is described in detail. The effect of the SiBN interlayer in reducing the second wiring capacitance is compared to that of a conventional silicon nitride interlayer. This is demonstrated by fabricating a 33-stage ECL ring oscillator and a 2.1 kG macrocell array LSI. >