Tetsushi Sakai

A new silicon‐on‐insulator structure using a silicon molecular beam epitaxial growth on porous silicon

A new silicon‐on‐insulator (SOI) structure has been achieved by utilizing silicon molecular beam epitaxial (Si‐MBE) growth on porous silicon, silicon island patterning, and the subsequent laterally enhanced oxidation of the porous silicon. The surface of Si‐MBE film grown on porous silicon at 770 °C without high‐temperature preheating has a 7×7 superlattice structure when observed by a reflection high‐energy electron diffraction (RHEED). Patterned Si‐MBE film island, that is 7.0 μm wide and 0.35 μm thick, is successfully isolated by the laterally enhanced oxidation of porous silicon.

Prospects of SST technology for high speed LSI

SST has realized very high speed integrated circuits with a basic gate delay time of 25.8 ps/gate. Also, a 10.38 GHz frequency divider, a 0.85 ns 1 Kb RAM and a 6 ns 16×16 bit parallel multiplier are fabricated using SST with 1um optical lithography. For a scaled-down SST transistor, the basic gate delay time is expected to be less than 10 ps/gate.

High performance LSI process technology: SST CBi-CMOS

A CBi-CMOS IC, with complementary high-performance bipolar and CMOS on the same wafer, is reported. The structure is based on a self-aligned high-speed bipolar process called super self-aligned process technology or SST. The fabrication process is described, and its feasibility is confirmed by evaluating some devices fabricated by this technology. With a single 5-V supply, a propagation time delay of 160 ps has been measured for a 1- mu m-gate-length CMOS ring oscillator. n-p-n and p-n-p transistors have also been fabricated with f/sub T/ values of 16.9 and 7.5 GHz, respectively.<<ETX>>

A 3-ns 1-kbit RAM using super self-aligned process technology

A high speed 1-kbit ECL RAM with a typical access time of 2.7 ns and power dissipation of 500 mW has been developed, using a novel LSI fabrication process technology, together with a new reference circuit configuration. This paper describes an integrated transistor structure using this novel process technology, fabrication steps, a new sense circuit and performance of the RAM.

Very-high f/sub T/ and f/sub max/ silicon bipolar transistors using ultra-high-performance super self-aligned process technology for low-energy and ultra-high-speed LSI's

Very-high f/sub T/ (up to 50 GHz) and f/sub max/ (up to 70 GHz) silicon bipolar transistors have been developed using Ultra-high-performance Super Self-aligned process Technology (USST). This technology is characterized by drastically-scaled lateral dimensions and shallow, heavily-doped extrinsic base structures. USST greatly reduces base-collector junction capacitance and base resistance, and hence makes f/sub max/ about twice as large as SST1C technology without vertical scaling. The fabricated ECL circuits show a minimum gate delay of 16.5 ps at a switching current of I/sub CS/=1.0 mA/G.

HSST BiCMOS technology with 26 ps ECL and 45 ps 2 V CMOS inverter

HSST/BiCMOS technology has been developed by merging a novel 0.3 mu m self-aligned double-poly bipolar process called high-performance super self-aligned process technology (HSST) and the 0.22 mu m CMOS process. The HSST bipolar transistor size is 2.5 times smaller than that of 1 mu m SST-1B with an emitter 0.4 mu m wide. This results from a 0.3 mu m design rule, a collector polysilicon trench electrode, and oxide-filled trench isolation. Owing to the horizontal shrinking and high cutoff frequency of 22.3 GHz at V/sub ce/=1 V, the ECL (emitter coupled logic) gate attains 25.4 ps/G at 1.58 mA. For the 0.2 mu m CMOS inverter, gate delays of 44.5 ps/G at V/sub dd/=2 V and 32.8 ps/G at 3 V are obtained. The BiCMOS gate also operates up to 116 ps/G at 2 V, 66.1 ps/G at 3 V, and 52.1 ps/G at 4 V.<<ETX>>

Stepped Electrode Transistor: SET

SET can achieve high performance without precise photolithography and metallization techniques. An arsenic doped polycrystalline silicon is used as a part of the emitter electrode in the SET structure. It is processed to have an inverse trapezoid shape. Procedure to make the inverse trapezoid shape uses a difference of etching rates between double layers of polycrystalline silicon. Base contact windows are opened through the ion-implantation process followed by chemical etching. The spacing between the emitter diffused layer and the base contact is as short as 0.4 µm or less. The cut off frequency of |S21e| is about 8.4 GHz. This frequency is higher than that of the conventional planar transistors with equal size emitter by 2 GHz. The rise time is 150 psec in the integrated SET.

The Effect of Nitrogen in a p + Polysilicon Gate on Boron Penetration Through the Gate Oxide

Effects of nitrogen in p + polysilicon gates on boron penetration into a silicon substrate through the gate oxide are studied. Four factors that might be involved in how nitrogen in the polysilicon gate suppresses boron penetration were investigated: first, boron diffusivity in the interior of the nitrogen-doped polysilicon film; second, segregation of boron at the polysilicon/SiO 2 interface; third, pileup of nitrogen at the polysilicon/SiO 2 interface; and fourth, boron diffusivity in SiO 2 decreased by incorporation of nitrogen into SiO 2 from polysilicon. From several experimental results, it was confirmed that the decrease in the boron diffusivity in the interior of the polysilicon gate is responsible for the suppression of boron penetration.

A 100 PS bipolar logic

AN ULTRA HIGH-SPEED bipolar integrated circuit has been developed with a propagation delay time of less than 100 ps. The process technologies involved are Elevated Electrode IC, an advanced version of SET’. The integrated transistor structure is shown in Figure 1. Arsenic doped polycrystalline silicon is used for the diffusion source as well as the elevated electrodes, emitter and collector, and also interconnection between devices. The polycrystalline silicon is processed to form an overhanging edge. In the subsequent metal evaporation process, the shadowed area under the overhanging edge functions to separate the polycrystalline silicon from the lower level, consequently the evaporated metals are isolated from another by the overhanging edge and the formation of all electrodes and interconnections is completed without the use of fine photolithography and etching processes. After the evaporation of metal on the entire surface of the circuit, the unnecessary portions are etched out by the conventional process, without precise mask alignment. The second metalization step can be made in the conventional way.

REDISTRIBUTION OF IN SITU DOPED OR ION-IMPLANTED NITROGEN IN POLYSILICON

This article reports a secondary ion mass spectroscopy analysis of the redistribution of in situ doped or implanted nitrogen in polysilicon and the segregation of nitrogen at the polysilicon/SiO2 interfaces during heat treatment at 700–1000 °C. When nitrogen‐doped polysilicon is subjected to heat treatment at a temperature above 800 °C, nitrogen diffuses to the poly‐Si/SiO2 interface and surface, and piles up there. Some of the nitrogen is immobile when the concentration is above a particular threshold concentration. This immobile nitrogen becomes mobile and diffuses during annealing. The threshold concentration for nitrogen diffusion depends on the grain size. There is a limit to how much nitrogen segregates to the interface. The limit depends not on the initial amount of nitrogen in the polysilicon, but only on the annealing temperature. A comparison of data for polysilicon films with data for bulk silicon suggests that the redistribution of nitrogen in the polysilicon films is limited by the transforma...