Shinya Fujioka
Fujitsu
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Publication
Featured researches published by Shinya Fujioka.
international solid-state circuits conference | 1997
Atsushi Hatakeyama; Hirohiko Mochizuki; Tadao Aikawa; Masato Takita; Yuki Ishii; Hironobu Tsuboi; Shinya Fujioka; Shusaku Yamaguchi; Makoto Koga; Yuji Serizawa; Koichi Nishimura; Kuninori Kawabata; Yoshinori Okajima; Michiari Kawano; Hideyuki Kojima; Kazuhiro Mizutani; Toru Anezaki; Masatomo Hasegawa; Masao Taguchi
This 256 Mb synchronous DRAM with 1 ns clock access is stable against temperature, voltage, and process variation by use of an innovative register-controlled delay locked loop (RDLL). Unlike most conventional high-density DRAMs, the bit-lines are placed above the storage capacitors in this DRAM to relax design rules of the core area. The noise issues are analyzed and resolved to help implement the technology in mass production of 0.28 to 0.24 /spl mu/m 200 MHz DRAMs.
Archive | 1996
Shinya Fujioka; Atsushi Hatakeyama; Hirohiko Mochizuki
Archive | 2013
Shinya Fujioka; Tomohiro Kawakubo; Koichi Nishimura; Kotoku Sato
Archive | 1999
Akihiro Funyu; Shinya Fujioka; Yasuharu Sato; Toshiya Uchida
Archive | 2000
Shinya Fujioka
Archive | 2000
Masato Matsumiya; Shinya Fujioka; Kimiaki Satoh; Toru Miyabo
Archive | 1999
Yasuharu Sato; Tadao Aikawa; Shinya Fujioka; Waichiro Fujieda; Hitoshi Ikeda; Hiroyuki Kobayashi
Archive | 2002
Shinya Fujioka; Waichiro Fujieda; Kota Hara; Toru Koga; Katsuhiro Mori
Archive | 1999
Shinya Fujioka
Archive | 1999
Shinya Fujioka; Masao C O Fujitsu Limited Taguchi; Yasuharu Sato; Takaaki Suzuki; Tadao Aikawa; Yasurou Matsuzaki; Toshiya Uchida
