Shinya Itoh

A Low-Noise High Intrascene Dynamic Range CMOS Image Sensor With a 13 to 19b Variable-Resolution Column-Parallel Folding-Integration/Cyclic ADC

A low temporal noise and high dynamic range CMOS image sensor is developed. A 1Mpixel CMOS image sensor with column-parallel folding-integration and cyclic ADCs has 80μV_rms (1.2e^-) temporal noise, 82 dB dynamic range using 64 samplings in the folding-integration ADC mode. Very high variable gray-scale resolution of 13b through 19b is attained by changing the number of samplings of pixel outputs. The implemented CMOS image sensor using a 0.18-μm technology has the sensitivity of 10-<i>V</i>/lx·s, the conversion gain of 67- μV/e^-, and linear digital code range of more than 4 decades.

A 16 Mb 400 MHz loadless CMOS four-transistor SRAM macro

0.18 /spl mu/m logic process technologies have recently been used to develop a loadless CMOS four-transistor SRAM cell (4T-cell) whose size (1.934 /spl mu/m/sup 2/) is only 56% that of a conventional six-transistor SRAM cell (6T-cell). Using this 4T-cell technology. The authors present a 16 Mb, 400 MHz SRAM macro which features: (1) an end-point dual-pulse driver (EDD) for stable data hold and minimum cycle time, (2) word-line-voltage-level compensation (WLC) for stable static data hold, and (3) an all-adjoining twist bit-line (ATBL) to reduce bit-line coupling capacitance.

Column-Parallel Correlated Multiple Sampling Circuits for CMOS Image Sensors and Their Noise Reduction Effects

For low-noise complementary metal-oxide-semiconductor (CMOS) image sensors, the reduction of pixel source follower noises is becoming very important. Column-parallel high-gain readout circuits are useful for low-noise CMOS image sensors. This paper presents column-parallel high-gain signal readout circuits, correlated multiple sampling (CMS) circuits and their noise reduction effects. In the CMS, the gain of the noise cancelling is controlled by the number of samplings. It has a similar effect to that of an amplified CDS for the thermal noise but is a little more effective for 1/f and RTS noises. Two types of the CMS with simple integration and folding integration are proposed. In the folding integration, the output signal swing is suppressed by a negative feedback using a comparator and one-bit D-to-A converter. The CMS circuit using the folding integration technique allows to realize a very low-noise level while maintaining a wide dynamic range. The noise reduction effects of their circuits have been investigated with a noise analysis and an implementation of a 1Mpixel pinned photodiode CMOS image sensor. Using 16 samplings, dynamic range of 59.4 dB and noise level of 1.9 e− for the simple integration CMS and 75 dB and 2.2 e− for the folding integration CMS, respectively, are obtained.

A CMOS Image Sensor With In-Pixel Two-Stage Charge Transfer for Fluorescence Lifetime Imaging

A CMOS image sensor for time-resolved fluorescence lifetime imaging with subnanosecond time resolution is presented. In order to analyze the fluorescence lifetime, the proposed CMOS image sensor has two charge transfer stages using a pinned photodiode structure in which the first charge transfer stage is for the time-resolved sifting of fluorescence in all the pixels simultaneously and the second charge transfer stage is for reading the signals in each pixel sequentially with correlated double sampling operation. A 0.18-mum CMOS image sensor technology with a pinned photodiode process option is used for the implementation of a 256 times 256 CMOS image sensor. The decaying images and lifetimes of fura-2 solutions having different concentrations are successfully measured with a 250-ps time step using the CMOS image sensor and ultraviolet laser diode as a light source.

A 2.7e- temporal noise 99.7% shutter efficiency 92dB dynamic range CMOS image sensor with dual global shutter pixels

A low-noise global shutter CMOS image sensor is a next challenge to expand the market for CMOS image sensors. A low-noise global electronic shutter can be used for various applications such as high-speed imaging, machine vision and mechanical shutterless digital still cameras. A commonly used five transistor (5T) global shutter pixel using a floating diffusion memory suffers from large temporal noise due to kTC noise (reset noise) and large dark current [1]. Two-stage charge transfer pixels such as a seven transistor (7T) active pixel [2] and a dual pinned-diode active pixel presented by the authors [3] cancel the kTC noise. However, such structures have an issue of low shutter efficiency due to leakage from a photodiode to storage gate or diode. Furthermore, the 7T pixel suffers from dark current and transfer noise because of the use of surface-channel storage gates. The dual pinned-diode pixel of the previous design has problem of non-linearity due to poor charge transfer efficiency from a photodiode to storage diode.

A Two-Stage Charge Transfer Active Pixel CMOS Image Sensor With Low-Noise Global Shuttering and a Dual-Shuttering Mode

A complementary metal-oxide-semiconductor (CMOS) image sensor with low-noise global shuttering and a dual-shuttering mode is presented. The developed two-stage charge transfer pixel enables noise canceling by means of true correlated double sampling. The implemented prototype demonstrates for the first time that a noise level of less than three electrons can be achieved in a global-shutter CMOS image sensor while attaining high shutter efficiency of 99.7%. In the dual-shuttering mode, both a pinned storage diode signal and a floating diffusion signal are used for desirable functions such as wide-dynamic-range imaging, motion detection, and dual consecutive snapshot imaging.

A CMOS image sensor for 10Mb/s 70m-range LED-based spatial optical communication

Spatial optical communication has recently been of interest in the mobile local-area communication systems, especially in the automotive applications. It has many advantages over the radio communication such as robustness to jamming, human safety due to lack of electromagnetic waves and sender finding function. The image sensor communication (ISC) technology is useful for the spatial optical communication because to find the light source and to intensify the light energy density at the receiver, the optical receiver has to have signal light source finding and tracking functions. A few approaches for the ISC have been reported. CMOS ISC chips have been used for ID beacon detection [1] [2], where very low data rate is required. In an ISC chip for optical wireless LAN application [3], the data rate of several hundreds of MHz has been demonstrated. In this approach, however, photo-diode current of a 2-D detector array directly flows into external receiver circuits, and because of this, extremely large optical power using laser lights is required. The authors have reported an ISC chip for LED-light communications [4]. In this chip, the bit rate of 1Mb/s and the communication range of a few meters only have been demonstrated. Though the chip claims the function of signal light source tracking, no experimental results have been shown. This paper presents a CMOS ISC chip which demonstrates that the high-speed long-distance spatial optical communication over 10Mb/s and 50meters are realized for the system using LED light sources while attaining signal-light finding and tracking functions. The key techniques to improve the data rate and tracking performance are a new pixel structure using depleted diode, pulse equalizing, and binary flag image readout to find the exact area of light source.

An 80μV rms -temporal-noise 82dB-dynamic-range CMOS Image Sensor with a 13-to-19b variable-resolution column-parallel folding-integration/cyclic ADC

Low-noise CMOS image sensors (CIS) employing column-parallel amplifiers that significantly reduce temporal noise, as well as electron-multiplication CCD (EM-CCD) image sensors are becoming popular for very-low-light-level imaging. These low-noise imagers with high-gain amplification in either the charge or voltage domains sacrifice the intra-scene dynamic range. Scientific applications of solid-state imagers strongly require very low temporal noise and wide intra-scene dynamic range as well as very high gray-scale resolution. A column-parallel analog-to-digital converter (ADC) and column-level signal processing in CISs are key techniques to meet these requirements. Single-slope [1,2], successive-approximation [3] and cyclic ADCs [4] are widely used for the column-parallel ADC in CMOS imagers. However, these ADCs require additional gain enhancements to achieve very low temporal noise. A recently reported [5] delta-sigma (ΔΣ) ADC has an attractive feature that low temporal noise and high resolution can be simultaneously attained by an oversampling technique. However, for very high resolution, a high number of samplings per pixel output, e.g., more than 360 samplings for 16b, is required.

A 2.6mW 2fps QVGA CMOS one-chip wireless camera with digital image transmission function for capsule endoscopes

This paper presents the design and implementation of a one-chip camera device for capsule endoscopes. A prototype image sensor chip which has 320 times 240 effective pixels was fabricated using 0.25 mum CMOS image sensor process. This experimental chip integrates functional circuits required for capsule endoscopes and digital image transmission function. The integrated functional blocks include an image array, a timing generator, a clock generator, a voltage regulator, a 10b cyclic A/D converter, and a BPSK modulator. It can be operated autonomously with 3 pins (VDD, GND, and DATAOUT). With a 2.0 V power supply, the analog part consumes 950muW and the total power consumption at 2 frames per second (fps) is 2.6mW. Error-free image transmission over a distance of 48cm at 2.5Mbps corresponding to 2fps has been succeeded with inductive coupling

A CMOS imager and 2-D light pulse receiver array for spatial optical communication

This paper presents a CMOS imager and 2-D Light Pulse Receiver (LPR) array for car-to-car and road-to-car spatial optical communication. Using the prototype sensor with 640×240 image pixels and 640×240 LPR cells implemented with 0.18μm CMOS technology. Both imaging and 60fps optical communication at the carrier frequency of 1MHz are successfully performed. The measured signal amplitude and the calculation results of photocurrent shows that the spatial optical communication up to 100m is possible.