Shiro Hine

A 209 k-transistor ECL gate array with RAM

The authors describe a gate array with an ECL (emitter-coupled-logic) cell structure for implementing a high-density configurable RAM. A unit based on a variable size cell is modified to achieve such a RAM. Every unit has an extra transistor buried under the power bus to eliminate area penalty. One memory bit is constructed using one buried transistor plus three transistors in a unit. An n-p-n transistor and a tap resistor load cell are employed for structural matching with the logic gates. Since the read current is supplied directly from the V/sub CC/ bus instead of the word line, the transistor size of the word-line driver is minimized. The standby and read currents are 120 mu A and 800 mu A, respectively. The decoder, sense amplifiers, and word-line drivers are implemented by logic gates. RAM size can be varied by each unit row; the bit increment is 144. The process employs double-polysilicon self-aligned technology with a silicide-base electrode of TiSi/sub 2/ and triple-layer metallization. The features of the gate array are listed.<<ETX>>

120 V BiC-DMOS process for the latest automotive and display applications

The new 0.5 /spl mu/m design rule 120 V class BiCMOS and DMOS (120 V BiC-DMOS) process is developed by slight modifications from the 90 V BiC-DMOS process. The extra-one mask is added to enforce the isolation. Moreover, all the 5 V 90 V class devices are still included in this process. Improved edge termination structure brings 135 V breakdown voltage and 0.41 /spl Omega/ mm/sup 2/ in DMOS (vertical). DMOS (full isolation type) is also realized by using the RESURF (reduced surface field) structure. The combination of p/sup -/ LDD (lightly doped drain) and rounded P well are used for 120 V PMOS and 120 V field PMOS.

A 5.8-ns 256-Kb BiCMOS TTL SRAM with T-Shaped bit line architecture

Presents a new bit line architecture named T-shaped bit line architecture (TSBA), which is suitable for high speed, high density, and/or large bit-wide configuration SRAMs. TSBA, utilizing orthogonal complimentary bit lines in parallel with the word lines, is the solution to bit line pitch constraint for direct bipolar column sensing. This TSBA is applied to a 256-Kb SRAM with a typical access time of 5.8 ns. To achieve access times below 6 ns, this SRAM employs a bipolar Darlington column sense amplifier, a hierarchical column decoding scheme, a data bus shielding layout combined with TSBA, and a 0.8- mu m BiCMOS technology. >