Atsushi Ohba

A 209 k-transistor ECL gate array with RAM

The authors describe a gate array with an ECL (emitter-coupled-logic) cell structure for implementing a high-density configurable RAM. A unit based on a variable size cell is modified to achieve such a RAM. Every unit has an extra transistor buried under the power bus to eliminate area penalty. One memory bit is constructed using one buried transistor plus three transistors in a unit. An n-p-n transistor and a tap resistor load cell are employed for structural matching with the logic gates. Since the read current is supplied directly from the V/sub CC/ bus instead of the word line, the transistor size of the word-line driver is minimized. The standby and read currents are 120 mu A and 800 mu A, respectively. The decoder, sense amplifiers, and word-line drivers are implemented by logic gates. RAM size can be varied by each unit row; the bit increment is 144. The process employs double-polysilicon self-aligned technology with a silicide-base electrode of TiSi/sub 2/ and triple-layer metallization. The features of the gate array are listed.<<ETX>>

A 7 ns 1 Mb BiCMOS ECL SRAM with shift redundancy

A 7-Mb BiCMOS ECL (emitter coupled logic) SRAM was fabricated in a 0.8 mu m BiCMOS process. An improved buffer with a high-level output of nearly V/sub CC/ is adopted to eliminate the DC current in the level converter circuit, and the PMOS transistor has a wide operating margin in the level converter. The configurable bit organization is realized by using a sense-amplifier switch circuit with no access degradation. A wired-OR demultiplexer for the *1 output, having the same critical path as the *4 output circuit, allows for the same access time between the two modes. The *1 or *4 mode is electrically selected by the external signal. A simplified programming redundancy technology, shift redundancy, is utilized. Address programming is performed by cutting only one fuse in the shift redundancy. The RAM operates at the ECL-10K level with an access time of 7 ns. and the power dissipation at 50 MHz is 600 mW for the * mode. >

A 5.8-ns 256-Kb BiCMOS TTL SRAM with T-Shaped bit line architecture

Presents a new bit line architecture named T-shaped bit line architecture (TSBA), which is suitable for high speed, high density, and/or large bit-wide configuration SRAMs. TSBA, utilizing orthogonal complimentary bit lines in parallel with the word lines, is the solution to bit line pitch constraint for direct bipolar column sensing. This TSBA is applied to a 256-Kb SRAM with a typical access time of 5.8 ns. To achieve access times below 6 ns, this SRAM employs a bipolar Darlington column sense amplifier, a hierarchical column decoding scheme, a data bus shielding layout combined with TSBA, and a 0.8- mu m BiCMOS technology. >

A macro analysis of soft errors in static RAMs

In the soft error phenomenon in static RAMs (SRAMs), the mechanism of data upset is more complicated than in dynamic RAMs (DRAMs) because the storage nodes in the memory cells are connected to the power supply via load element. Therefore the critical charge has been evaluated only by computer simulation. The charge which is supplied via load element is estimated analytically, assuming alpha -particle-induced current being constant. The charge which is fed through the load element contributes to the increase of the critical charge in a 1-kbit emitter-coupled logic (ECL) RAM with a 10-k Omega resistor load. In ECL RAMs or MOS SRAMs with a larger resistor, the contribution of the charge which is fed through the load element is hardly expected, and the critical change in such RAMs is evaluated by the stored charge like DRAMs. >

New decoding architecture to reduce peak current and its implementation to 4 M ECL SRAM

The authors describe the multitiming buffering architecture (MTBA) and the pseudo hierarchical word decoding architecture (pseudo-HWD). These architectures have been implemented on a 4M emitter-coupled logic (ECL) SRAM with a 0.6- mu m BiCMOS process, and have effectively reduced the peak current of the decoding circuit by 32% and maximum di/dt by 63%, as compared with the three-level HWD. The SRAM achieved a 7-ns access time and a 160-mA active current at 50 MHz.<<ETX>>

New bit line architecture for ultra high speed SRAMs-T-shaped bit line and its real application to 256 k BiCMOS TTL SRAM

The authors propose a novel bit line architecture, the T-shaped bit line architecture (TSBA), which is suitable for high-speed, high-density and/or large bit-wide configuration SRAMs (static random-access memories). This architecture is applied to 256-kb BiCMOS TTL (transistor-transistor logic) I/O SRAM with a typical access time of 5.8 ns. To achieve sub-6-ns access time, a bipolar Darlington column sense amplifier, a global column decode technique, a shielded data bus technique with TSBA, and 0.8- mu m BiCMOS technology are employed.<<ETX>>

0.6-amu;m 12 K-gate ECL gate array with RAM and ROM

A 12 K-gate ECL (emitter-coupled logic) gate array with dedicated memory has been developed using 0.6-μm bipolar process technology. The memory is available for RAM or ROM storage. The gate array can also be used to implement a configurable RAM having internal cells