Shiwei Cheng

A wide band differentially switch-tuned CMOS monolithic quadrature VCO with a low Kvco and high linearity

A wide band, differentially switch-tuned CMOS monolithic LC-VCO is presented in this paper, as well as a frequency divider for high linearity, low Kvco quadrature signal generation. A linearity control logic is proposed. The Kvco linearity is improved to be lower than 17.68MHz/V. By using the proposed CML DFF, the operating frequency of the frequency divider is increased by 20% with a power consumption of 3.6mW. The proposed design has been fabricated and verified in a 0.18@mm CMOS process. The QVCO is tuned in a combined way of continuous technology and 4bit binary switch capacitor array (SCA) discrete tuning technology. The measurement indicates that the QVCO has a 19.7% tuning range from 1.816 to 2.213GHz. The measured phase noise is -112.25dBc/Hz at 1MHz offset from the 1.819GHz carrier and draws a current of 4.0mA around at a 1.8V supply.

A Δ-Σ fractional-N frequency synthesiser with quantisation noise folding suppression

A wideband Δ-Σ fractional-N frequency synthesiser with novel Δ-Σ quantisation noise folding suppression technique is presented in this article. A novel linearisation technique is proposed to suppress Δ-Σ quantisation noise folding due to nonlinearity of the phase frequency detector/charge pump (PFD/CP). In order to cover a wide frequency band and process, voltage and temperature (PVT) variation, a switched capacitors LC tank voltage-controlled oscillator and closed-loop automatic frequency band selection method are adopted. The chip is fabricated in a HeJian 0.18 radio frequency (RF) CMOS process. The measured output frequency is from 1.75 to 2.25 GHz with tuning range as wide as 500 MHz. The measured phase noise performance is −81.97 dBc/Hz and −112 dBc/Hz at 10-KHz and 1-MHz offset frequency, respectively. The measured reference spur is −44.05 dBc/Hz at 10-MHz offset frequency. The frequency synthesiser consumes 27.8 mW from a 1.8 V power supply.

A 0.18um 3.3mW double-balanced CMOS active mixer

This paper introduces a Gilbert-type active CMOS mixer integrated in 0.18 um process. Radio frequency signals are feed to the input ports of mixer, and then down-converted to IF band of 1 MHz. No inductor is employed in this circuit to reduce the circuit size. The circuit requires a 1.8 V voltage source and consumes only 3.3 mW when in normal mode. With gain increasing strategy, simulation results indicate the active mixer has a conversion gain of 6.2 dB, IIP3 of -4.4 dBm, noise figure of 12.8 dB.It is suitable for low-power frequency translation applications.

A CMOS polyphase low-IF filter with on-chip frequency control

A CMOS polyphase low-IF filter with on-chip frequency control for a 2.4 GHz wireless LAN is presented. Designed in a 1.8 V, 0.18 mum standard CMOS process, this Chebyshev polyphase filter has a 7th order 0.5 dB passband ripple. An on-chip auto frequency control module is designed for the variation of process in order to get the required sensitivity of the filter. This filter consumes 1.74 mW including the on-chip control module and the total chip area is 0.276 mm2.

A 2.4-GHz spur-cancelled fractional-n frequency synthesizer with PFD/DAC structure for WSN application

A 2.4-GHz wideband fractional-N frequency synthesizer utilizing PFD/DAC structure for Wireless Sensor Network (WSN) Application is presented. In this synthesizer, hybrid of phase/frequency detector and compensated digital-to-analog converter (PFD/DAC) is utilized to achieve phase noise performance as an integer-N synthesizer. The synthesizer is implemented with wide 400 kHz loop bandwidth and 4 us setting time. The chip occupies 1.9 mm2 and consumes 16.4 mA at 1.8-V supply.

Effect of structural parameters on the performance and variations of nanosizes PNIN tunneling field effect transistor

The characteristics of PNIN tunneling field effect transistor (TFET) with nanometer sizes are investigated using TCAD simulation. The results show that the performance and variations of the device strongly depends on the key parameters such as the thickness and the doping of the middle N layer. (1) An increase in the thickness of the N layer to ∼5 nm will effectively enhance the drive current, reduce the electric field normal to the Si/SiO2 interface (Ex), and reduce the variation of the threshold voltage induced by the variation in the N layer thickness. (2) A decrease in the thickness of Si film down to ∼5 nm will also reduce Ex, but with minor effect on the on current. Therefore, the overall characteristic of PNIN devices improves with reducing the Tsi. (3) A proper doping such as ∼2×1019 cm−3 in the N layer can remove the dependence and therefore the variation of the threshold voltage on the thickness of Si film.

A pseudo-Gaussian filter and sigma-delta modulator for IEEE 802.11a/b/g transmitter

This paper presents two components of an indirect modulation transmitter: a low-cost pseudo-Gaussian filter (PGF) and a modified third-order sigma-delta modulator (SDM) for WLAN 802.11a/b/g or Bluetooth. The PGF is a Gaussian filter quantized with 4 bits and is implemented using look up table method. The SDM is a modified feed forward third order modulator with local feedback to enhance signal-to-noise ratio (SNR). With a reference clock of 16 Mhz frequency, the components are designed to work at a transmission rate of up to 1 Msymbols/s. Simulation results show that the circuits work well and the noise is less than -90 dB at 3 Mhz offset frequency. The combination of the two circuits is implemented in 0.18-um CMOS technology, occupying an area of 147 um X 147 um.

A 2.4GHz highly linear class C power amplifier in 0.18 μ m CMOS technology

This paper presents a class C power amplifier (PA) with high efficiency and linearity , implemented in 0.18 mum CMOS technology. The third harmonic is controlled by Biasing while the second harmonic is limited by employing the differential structure. It delivers a power gain of 19.7 dB at the input power of -12 dBm with power added efficiency (PAE) of 43%. The second and third harmonics are -35.1 dBc and -36.0 dBc. In order to drive a single-ended load, an off-chip balanced-unbalanced (balun) circuit is also designed and analyzed in this paper.