Shobhit Malik

Identifying systematic critical features using silicon diagnosis data

A production worthy methodology has been outlined that uses layout aware scan diagnosis data to validate whether certain topologies are design-process induced defects. The methodology uses pattern matching technology to generate a set of critical feature hypotheses and uses diagnosis-driven yield analysis to validate or refute the hypotheses. The methodology is demonstrated in a 28nm GLOBALFOUNDRIES yield ramp to uniquely identify systematic critical features in silicon and provide a best description of the surrounding topology which induces the defect, along with quantifying the yield impact.

Framework for identifying recommended rules and DFM scoring model to improve manufacturability of sub-20nm layout design

This paper addresses the framework for building critical recommended rules and a methodology for devising scoring models using simulation or silicon data. Recommended rules need to be applied to critical layout configurations (edge or polygon based geometric relations), which can cause yield issues depending on layout context and process variability. Determining of critical recommended rules is the first step for this framework. Based on process specifications and design rule calculations, recommended rules are characterized by evaluating the manufacturability response to improvements in a layout-dependent parameter. This study is applied to critical 20nm recommended rules. In order to enable the scoring of layouts, this paper also discusses a CAD framework involved in supporting use-models for improving the DFM-compliance of a physical design.

Automated yield enhancements implementation on full 28nm chip: challenges and statistics

This paper shares the details of the Yield Enhancements that were done at 28nm full chip level sharing the complexity involved in implementing such a flow and then the verification challenges involved , e.g., at mask data preparation. We discuss and present the algorithm used to measure the efficiency of the tool, explaining why we used this algorithm while sharing some alternate algorithms possible. We also share the detailed statistics regarding run time, machine resource, data size, polygon counts etc. We also present good techniques used by us for efficient flow management involved in large complex 28nm chips.

Deriving Feature Fail Rate from Silicon Volume Diagnostics Data

In this paper, we propose expanding the use of volume diagnostics to go beyond the identification of critical features to accurately estimate their FFRs. We present a case study where FFRs of a few critical features are identified using volume diagnostics. We also compare FFRs calculated from volume diagnostics to those extracted for the same feature on test structures, which validates our presented approach.

Yield enhancement flow for analog and full custom designs reliability-rules automatic application

As the variations of shrunk processes increase at rapid rate, the performance of fabricated analog and full custom chips remarkably fluctuate. This paper describes an effective automatic flow for reliability rules automatic application onto analog and full-custom ASIC designs, without introducing any new design rules check (DRC) violations in input design. This Yield enhancement flow has shown good improvements on used test designs, and ran in reasonable time. Based on the standardization methodology used, additional foundry Yield-enhancement-related recommendations can be also developed as extension to this flow seamlessly providing easy and quick new technology adoption and short Turnaround Time (TAT).

Quantified contribution of design for manufacturing to yield at 28nm

Yield is the single most important criterion which drives the economics of our industry, impacting the bottom line directly. It is a well understood fact that both foundries and fabless companies have an extremely strong interest in achieving high yield as quickly as possible to meet the economies of scale and rapid time to market. At the 28nm node and below, implementation of DFM is believed to be particularly critical to enable a fast yield ramp. Quantification of the yield impact of various DFM enhancements is crucial to drive the appropriate design tradeoffs. In this paper we present an analysis of yield impact of DFM features over the duration of technology and product yield ramp for the 28nm node. Yield has inherent variation due to nature of its dependency on multiple factors and stages which makes it difficult to attribute yield signal to a small action in a long chain of event, from design to fabrication, leading to successful yield. We created a set of designs in 28nm, with and without DFM, where DFM changes were done only opportunistically. After finishing these designs, both the unmodified and the DFM enhanced layouts were placed side by side on the test chip reticles. Both instances got tested over long time for yield evaluation on silicon to create enormous amount of data which we analyzed and present in this paper. For analysis of all this data, we compare different statistical methods to understand the same and present challenges faced using these methods. We conclude with successful application of Matched Pair statistical method that quantified yield sensitivity to the DFM design changes.

Decomposition-aware layout optimization for 20/14nm standard cells

Decomposition-aware layout design improvements for 8, 9, 11, and 13-track 20/14nm standard cells are presented. Using a decomposition-aware scoring methodology that quantifies the manufacturability of layouts, the Double Patterning Technology (DPT)-compliant layouts are optimized for DPT-specific metrics that include: the density difference between the two decomposition mask layers, the enclosure of stitching areas, the density of stitches, and the design regularity of stitching areas. For a 9-track standard cell, eliminating the stitches from the layout design improved the composite score from 0.53 to 0.70.

Enhanced layout optimization of sub-45nm standard: memory cells and its effects

Automatic layout optimization is becoming an important component of the DfM work flow, as the number of recommended rules and the increasing complexity of trade-offs between them makes manual optimization increasingly difficult and time-consuming. Automation is rapidly becoming the best consistent way to get quantifiable DfM improvements, with their inherent yield and performance benefits for standard cells and memory blocks. Takumi autofixer optimization of Common Platform layouts resulted in improved parametric tolerance and improved DfM metrics, while the cell architecture (size and routability) and the electrical characteristics (speed/power) of the layouts remained intact. Optimization was performed on both GDS-style layouts for standard cells, and on CDBA (Cadence Data Base Architecture)-style layout for memory blocks. This paper will show how trade-offs between various DfM requirements (CAA, recommended rules, and litho) were implemented, and how optimization for memories generated by a compiler was accomplished. Results from this optimization work were verified on 45nm design by model and rule based DfM checking and by wafer yields.

Quantifying electrical impacts on redundant wire insertion in 7nm unidirectional designs

In nano-meter scale Integrated Circuits, via fails due to random defects is a well-known yield detractor, and via redundancy insertion is a common method to help enhance semiconductors yield. For the case of Self Aligned Double Patterning (SADP), which might require unidirectional design layers as in the case of some advanced technology nodes, the conventional methods of inserting redundant vias don’t work any longer. This is because adding redundant vias conventionally requires adding metal shapes in the non-preferred direction, which will violate the SADP design constraints in that case. Therefore, such metal layers fabricated using unidirectional SADP require an alternative method for providing the needed redundancy. This paper proposes a post-layout Design for Manufacturability (DFM) redundancy insertion method tailored for the design requirements introduced by unidirectional metal layers. The proposed method adds redundant wires in the preferred direction - after searching for nearby vacant routing tracks - in order to provide redundant paths for electrical signals. This method opportunistically adds robustness against failures due to silicon defects without impacting area or incurring new design rule violations. Implementation details of this redundancy insertion method will be explained in this paper. One known challenge with similar DFM layout fixing methods is the possible introduction of undesired electrical impact, causing other unintentional failures in design functionality. In this paper, a study is presented to quantify the electrical impacts of such redundancy insertion scheme and to examine if that electrical impact can be tolerated. The paper will show results to evaluate DFM insertion rates and corresponding electrical impact for a given design utilization and maximum inserted wire length. Parasitic extraction and static timing analysis results will be presented. A typical digital design implemented using GLOBALFOUNDRIES 7nm technology is used for demonstration. The provided results can help evaluate such extensive DFM insertion method from an electrical standpoint. Furthermore, the results could provide guidance on how to implement the proposed method of adding electrical redundancy such that intolerable electrical impacts could be avoided.

DiagBridge: Analyzing scan diagnosis data in a yield perspective

In this work, we described a powerful volume diagnosis and yield analysis framework called DiagBridge. DiagBridge enhances volume diagnosis results with sort and design data so as to present the volume diagnosis results in easy-to-understand metrics like yield loss estimation and failure rate estimation. We are already sharing these results with cross-functional teams and seeing various functional teams taking corrective actions to improve yield and reduce yield-limiting factors. Such systems further enables straight-forward comparisons and significantly improves the efficiency in logic yield ramping.