Shoichi Suda

The influence of the size effect of copper interconnects on RC delay variability beyond 45nm technology

We tried to evaluate and predict the RC delay variability beyond the 45 nm copper interconnects technologies. The RC delay variability as a normalized delay time distribution, is caused by the line width/height variations due to the manufacturing process fluctuations. In order to evaluate the influence of the resistivity size effect precisely, we improved Fuchs-Sondheimer (F-S) and Mayadas-Shatzkes (M-S) models, in order to include the line height dependence of copper grain size, and applied it in the evaluation of the RC delay variability based on the SPICE simulation. In our results, we found that the RC delay variability in the 45nm node technology was relatively small, weakly dependent on the grid size and line height, and almost not affected by the size effect. On the contrary, in the 32 nm technology, the RC delay variability was about 2 times larger than the case ignoring the size effect and reached to the 20% of the average delay time at 3000 grid with 10% of line size fluctuation. In the 32 nm technology, the line height dependence of the RC delay variability was also strong and increased with decreasing line height. The influence of line height dependence of grain size reached about 1/5 or more of the total size effect in the RC delay variability.

Development of highly reliable Cu wiring of L/S=1/1µm for chip to chip interconnection

Highly dense and reliable Cu wiring of L/S=1/1μm for chip to chip interconnection was developed, by improving the semi-additive process To meet the reliability requirements, a mechanism for leakage failures in the HAST environment was identified, and the improved processes for suppressing Cu corrosion and diffusion were established by reducing halogen ions and covering with metal cap barriers.