Shosuke Fujii

Highly Scalable Horizontal Channel 3-D NAND Memory Excellent in Compatibility With Conventional Fabrication Technology

We developed a stacked horizontal channel type floating gate (HC-FG) NAND memory; a 3-D stacked NAND array composed of conventional FG cells. With this cell structure, a wide program/erase (P/E) window is obtained, accompanied by superior read disturb immunity, P/E endurance, and data retention. In addition, we propose a low-cost layer select transistor (LST) that is easily integrated with the HC-FG cell. Because the 3-D memory composed of the HC-FG cell and the LST has good compatibility with conventional fabrication technology, further bit cost scaling is expected.

Transition of erase mechanism for MONOS memory depending on SiN composition and its impact on cycling degradation

We clarify the origin of erase improvement in MONOS memories with Si-rich SiN layer, and investigate the impact of erase mechanism on cycling degradation. It is demonstrated that cycling degradation is uniquely determined by charges injected during erase operations irrespective of program/erase condition, number of program/erase cycling, or MONOS structure.

First demonstration and performance improvement of ferroelectric HfO 2 -based resistive switch with low operation current and intrinsic diode property

We demonstrate, for the first time, a CMOS compatible ferroelectric HfO2-based two-terminal non-volatile resistive switch; HfO2 ferroelectric tunnel junction (FTJ). The device has characteristics of nA-range operation current, self-compliance, and intrinsic diode properties, as well as good device to device uniformity. Simultaneous achievement of these characteristics, which was not reported in the other two-terminal emerging memories, is significant advantage for future non-volatile applications. Accurate understanding of switching mechanism based on first-principles calculations and material characterization enabled us to establish a solid guideline for performance improvement: scaling of both ferroelectric layer and interfacial layer thickness. As a consequence, reduction of operation voltage while maintaining sufficient ON/OFF ratio was successfully demonstrated.

Interface State in Metal-Oxide-Nitride-Silicon Memories Induced by Hole Injection during Program/Erase Cycle Stress

The mechanism of interface-state generation in metal–oxide–nitride–silicon (MONOS) memories by program/erase (P/E) cycling was experimentally examined, using the charge measurement technique we developed that allows direct measurement of the amount of charges flowing during P/E operation. The amount of interface state was found to have a strong correlation with the amount of charges flowing during erase operation, irrespective of pulse voltage, pulse width and number of P/E cycles. It was also found that the amount of interface states generated by P/E cycling increases as hole fluence dominates erase operation. These findings suggest that hole injection from Si substrate, rather than electron detrapping from SiN layer or impact-ionized hot hole, is the main cause of the interface-state generation.

Precise understanding of data retention mechanisms for MONOS memories: Toward simultaneous improvement of retention and endurance performances by SiN engineering

We investigate the charge leakage path during data retention through the evaluation of its temperature dependence. As a result, it is experimentally demonstrated for the first time that the main leakage path of trapped charge changes depending on retention time. Furthermore, the direction of leakage path rather than trap energy profile in the SiN layer determines the temperature dependence of data retention characteristics. In addition, it is found that cycling degradation of data retention is due to increase in the charge loss through the tunnel layer. Based on the accurate understanding of data retention mechanisms, we show the possibility to achieve both of data retention and endurance improvements by SiN engineering.

A New Method to Extract the Charge Centroid in the Program Operation of MONOS memories

Introduction MONOS type device is a candidate to replace conventional floating gate (FG) non-volatile memory devices because of its low program/erase (P/E) voltage and reduced cell-to-cell interference effect. Instead of poly silicon FG, silicon nitride (SiN), which has discrete traps distributed in the thickness direction, is employed as a charge trap layer of MONOS devices. Then, the information about vertical position of trapped charge is important to understand the trapping properties of SiN layer and to improve the performance and reliability of MONOS devices. Although several techniques for charge centroid evaluation are proposed [1-4], some of these techniques require special device structures such as MONOS with lightly doped poly Si gate [3] or very thick (~50nm) SiN layer [4]. Three-level pulse method [1] is a relatively simple technique among the existing methods in the sense that it uses an ordinary MONOS structure, but this method demands a measurement of P/E characteristics in advance. Here, we present a new simple measurement technique to extract the charge centroid in the nitride layer during the program operation that improves the three-level pulse method.

Impact of program/erase stress induced hole current on data retention degradation for MONOS memories

We investigate the mechanism for the data retention degradation caused by program/erase (P/E) cycling in MONOS memories, using the carrier separation measurement to identify the carrier type of Stress-Induced Leakage Current (SILC). It is thereby found that SILC is composed mainly of holes for the MONOS with less Si-rich SiN layer (hole SILC). A clear correlation is also discovered between hole SILC and interface states generated during P/E cycle. We also discuss the mechanism of the degradation by hole SILC of the data retention characteristics of MONOS devices.

Dual nature of metal gate electrode effects on BTI and dielectric breakdown in TaC/HfSiON MISFETs

We investigated bias temperature instability (BTI) and time dependent dielectric breakdown (TDDB) in TaCx/HfSiON MOSFETs in terms of the effects of TaCx metal gate electrode, using various Ta composition and TaCx thickness. We find a dual nature of TaCx metal gate electrode effects on the reliability. The gate electrode has both positive and negative influence on BTI and TDDB. Though various TaCx layers were deposited on the same HfSiON layer, high composition of Ta in the TaCx layer and thick TaCx layer improve BTI and mobility, while they deteriorate time to breakdown (Tbd) because of the effects of metal gate induced defects.

Direct Measurement of Back-Tunneling Current during Program/Erase Operation of MONOS Memories and Its Dependence on Gate Work Function

Introduction MONOS memory is one of the candidates to replace floating gate (FG) non-volatile memory with its simple structure and less cell-to-cell interference [1]. Although multi-level cell operation is expected in MONOS memories to realize high density data storage, leakage current and back-tunneling current during program/erase (P/E) operation bring about Vth saturation [2] and narrow Vth window. Besides, it is known that penetration current severely degrades device reliability [3]. Thus, it is necessary to analyze current components of MONOS devices. Based on the charge-centroid extraction method [4][5], we have developed an analysis method which enables extracting back tunneling current component. In this paper, gate work function dependence of back-tunneling current during P/E operation is discussed to confirm the validity of our analysis scheme.

MONOS specific interface state generation/recovery mechanisms and their impact on reliability properties

Mechanisms of interface-state generation/recovery in MONOS memories were investigated. We found that the interface states are mostly due to Si-H bonds breakage, and that additional reactive species, which could be attributable to above-stacked SiN layer, are supplied to the interface during baking and passivate interface states, leading to the strengthened bond structure against electrical stress. These findings indicate that reliability properties can be improved by applying appropriate electrical stress and baking owing to replacement of Si-H to stronger bond.