Kiwamu Sakuma

Investigation of Nitrogen-Originated NBTI Mechanism in SiON with High-Nitrogen Concentration

We have investigated the nitrogen-originated NBT degradation mechanism of SiON films by using SiON with high nitrogen concentration. It was found that, threshold voltage shift (DeltaVth) under NBT stress is degraded with increasing nitrogen concentration in bulk rather than that at interface. Furthermore, NBTI exponents strongly correlate with the nitrogen concentration in bulk and pre-stressed flat-band voltage shift (AVfb ini). From these experimental results, we interpret that there is an additional NBT degradation mechanism with small NBTI exponents (beta > 0.25) and this is originated by pre-existing defects due to nitrogen incorporation. Finally, from the reliability viewpoint, we propose that decreasing the defect in bulk introduced during nitridation is indispensable for the fabrication process of high nitrogen concentration SiON maintaining high reliability

Highly Scalable Horizontal Channel 3-D NAND Memory Excellent in Compatibility With Conventional Fabrication Technology

We developed a stacked horizontal channel type floating gate (HC-FG) NAND memory; a 3-D stacked NAND array composed of conventional FG cells. With this cell structure, a wide program/erase (P/E) window is obtained, accompanied by superior read disturb immunity, P/E endurance, and data retention. In addition, we propose a low-cost layer select transistor (LST) that is easily integrated with the HC-FG cell. Because the 3-D memory composed of the HC-FG cell and the LST has good compatibility with conventional fabrication technology, further bit cost scaling is expected.

Improvement of erase-retention trade-off in metal–oxide–nitride–oxide–silicon memories by control of nitrogen profile in SiN charge-trapping layer

An improvement of the trade-off between erase speed and data retention characteristics in metal–oxide–nitride–oxide–silicon (MONOS) charge-trap-type flash memories is demonstrated by surface modification of the SiN charge-trapping layer. A SiN composition profile suitable for the nonuniform distribution of trapped electrons is realized by N2 plasma treatment of highly Si-rich SiN, which leads to a sufficient erase speed while improving data retention characteristics.

Reliability improvement in planar MONOS cell for 20nm-node multi-level NAND Flash memory and beyond

20nm-node planar MONOS cell which has improved reliability is developed. Extremely wide program/erase Vth window and good retention characteristics after cycling stress are obtained by buried charge cell structure. Moreover, Vth shift by interference between adjacent cells has smaller dependence on the cell-cell space than Vth window improvement when the half pitch is constant. These results show that the buried charge planar MONOS cell is suitable for Flash memory with 20nm-node and beyond.

Carrier transport analysis of high-performance poly-Si Nanowire transistor fabricated by advanced SPC with record-high electron mobility

This paper presents the fundamental carrier transport analysis of high-mobility poly-Si nanowire transistors (NW Tr). By adopting advanced SPC (solid-phase crystallization) process, record-high electron mobility (192cm2/Vs) and Ion (200μA/μm) at Ioff of 4nA/μm are achieved without using lasers or catalysts. Carrier density and temperature dependence of mobility, and also physical analysis of poly-Si crystallinity and the channel size, reveal that the origin of mobility degradation in conventional SPC poly-Si Tr. is Coulomb scattering due to defects inside grains as well as defects at grain boundaries and enhanced surface roughness scattering at poly-Si/gate oxide interface, all of which are weakened by advanced SPC process. At high carrier density, mobility of poly-Si nFETs and pFETs by advanced SPC process even exceeds bulk-Si (110) nFETs and (100) pFETs.

Silicon-compatible low resistance S/D technologies for high-performance top-gate self-aligned InGaZnO TFTs with UTBB (ultra-thin body and BOX) structures

We have fabricated high-performance self-aligned top-gate InGaZnO TFTs with novel silicon-like source and drain (S/D) parasitic resistance (RSD) reduction processes. Ar ion implantation (Ar I/I) formed S/D extension layers and reduced RSD by inducing high-density carriers. First demonstration of self-aligned S/D metallization processes on InGaZnO surface (In-Ti alloy formation), just like silicidation, realized further RSD reduction. In addition, threshold voltage (Vth) controllability by back-gate bias was enhanced by adopting thin InGaZnO body and BOX. Successful applications of these booster technologies developed for Si LSIs enable us to fabricate high-performance top-gate scaled InGaZnO TFT in 3D LSI.

Physical mechanism of source and drain resistance reduction for high-performance short-channel InGaZnO thin-film transistors

We systematically study the mechanism of source and drain parasitic resistance reduction in amorphous InGaZnO thin-film transistors. Hall measurement shows that parasitic resistance is reduced by the increase in carrier density regardless of the source and drain processes. The results of photoluminescence, high-angle annular dark field scanning transmission electron microscope (HAADF-STEM), electron energy-loss spectroscopy (EELS), and X-ray photoelectron spectroscopy (XPS) analyses indicate that the fluctuation of In concentration at the InGaZnO surface is responsible for increase in carrier density. A top-gate InGaZnO transistor fabricated with a source drain resistance reduction process shows good short-channel immunity. The short-channel InGaZnO thin-film transistor with reduced source drain resistance is promising as the high-density back-end-of-line transistor in Si LSI.

Impact of program/erase stress induced hole current on data retention degradation for MONOS memories

We investigate the mechanism for the data retention degradation caused by program/erase (P/E) cycling in MONOS memories, using the carrier separation measurement to identify the carrier type of Stress-Induced Leakage Current (SILC). It is thereby found that SILC is composed mainly of holes for the MONOS with less Si-rich SiN layer (hole SILC). A clear correlation is also discovered between hole SILC and interface states generated during P/E cycle. We also discuss the mechanism of the degradation by hole SILC of the data retention characteristics of MONOS devices.

One-to-one correspondence between nm-resolution channel crystallinity and electrical property of poly-Si TFT revealed by NBD two-dimensional imaging

We successfully established the direct correspondence between the whole channel crystallinity at nm-scale and electrical property in one and the same poly-Si thin-film transistors (TFTs). A low-damage focused ion beam (FIB) technique was newly developed for preparing site-specific nanobeam diffraction (NBD) specimen of bare channel of the TFT that was electrically evaluated in advance. We applied NBD two-dimensional imaging (2D1) to the whole channel area for acquiring massive diffraction patterns over 30,000 so that both high spatial resolution (3 nm) and large-area measurement (0.5×0.5 μm2) are achieved. Our NBD-2D1 analysis definitely revealed that drain current in individual TFTs is determined by whether the electrons can travel from the source to the drain without passing through the grain boundaries inside the channel, which cannot be clearly judged by using conventional scanning/ transmission electron microscopy (S/TEM) techniques.

Understanding of carrier transport in high-performance solid phase crystallized poly-Si nano-wire transistors

High-performance poly-Si nano-wire transistors were fabricated by Advanced SPC process, that consists of optimized a-Si deposition, crystallization annealing and poly-Si thinning processes. In order to determine what the dominant factor of scattering mechanism is, carrier mobility behavior at each temperature and surface carrier density (Ns) are fully investigated. It reveals that the hole mobility is dominated by phonon scattering in wide Ns regime. On the other hand, it is suggested that the electron mobility is dominated by Coulomb scattering by defects inside grains at low Ns and surface roughness scattering at high Ns.