Haruka Kusai

Highly Scalable Horizontal Channel 3-D NAND Memory Excellent in Compatibility With Conventional Fabrication Technology

We developed a stacked horizontal channel type floating gate (HC-FG) NAND memory; a 3-D stacked NAND array composed of conventional FG cells. With this cell structure, a wide program/erase (P/E) window is obtained, accompanied by superior read disturb immunity, P/E endurance, and data retention. In addition, we propose a low-cost layer select transistor (LST) that is easily integrated with the HC-FG cell. Because the 3-D memory composed of the HC-FG cell and the LST has good compatibility with conventional fabrication technology, further bit cost scaling is expected.

Improvement of erase-retention trade-off in metal–oxide–nitride–oxide–silicon memories by control of nitrogen profile in SiN charge-trapping layer

An improvement of the trade-off between erase speed and data retention characteristics in metal–oxide–nitride–oxide–silicon (MONOS) charge-trap-type flash memories is demonstrated by surface modification of the SiN charge-trapping layer. A SiN composition profile suitable for the nonuniform distribution of trapped electrons is realized by N2 plasma treatment of highly Si-rich SiN, which leads to a sufficient erase speed while improving data retention characteristics.

Impact of program/erase stress induced hole current on data retention degradation for MONOS memories

We investigate the mechanism for the data retention degradation caused by program/erase (P/E) cycling in MONOS memories, using the carrier separation measurement to identify the carrier type of Stress-Induced Leakage Current (SILC). It is thereby found that SILC is composed mainly of holes for the MONOS with less Si-rich SiN layer (hole SILC). A clear correlation is also discovered between hole SILC and interface states generated during P/E cycle. We also discuss the mechanism of the degradation by hole SILC of the data retention characteristics of MONOS devices.

Re-Examination of Performance and Reliability Degradation in Metal?Oxide?Nitride?Oxide?Semiconductor Memory with Ultrathin SiN Charge Trap Layers

We demonstrated that the degradation of program characteristics in metal–oxide–nitride–oxide–semiconductor (MONOS) devices consisting of an ultrathin (~2 nm) SiN charge trap layer is due to a decrease in the electron capture efficiency, instead of a reduction in the number of available trap sites. From the data retention properties with applied gate bias voltage, we clarified that charge loss through the tunnel layer during data retention becomes more significant with decreasing SiN thickness. These results indicate that to improve the performance and reliability of MONOS devices with an ultrathin SiN charge trap layer, measures must be taken to enhance the capture cross section of the traps and to inhibit carrier motion in the SiN layer simultaneously.