Shouzou Hirano

An EMI-noise analysis on LSI design with impedance estimation

The EMI noise of LSI has become more significant factor for LSI reliability. The result of a transistor-level simulator was not compared sufficiently with measurement and needs the final layout. This paper shows an EMI-noise analysis method at the early stage of the LSI design. The spectrum of the power supply current and the frequency response of the LSI estimated impedance are merged analytically at high speed. The current can be calculated at high speed by a gate level simulator with a triangle model. The experimental results show that our method has a high accuracy that is correlated with measurement results. Furthermore, the estimation method of the LSI impedance enables EMI noise prediction at the early stage of LSI design. The information obtained from our method can also help designers to improve LSI and electronic systems design quality.