Takahiro Ichinomiya

Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation*This study is a part of results in JEITA EDA technical special committee.

SUMMARY In this letter, we discuss the impact of intrinsic error in parasitic capacitance extraction programs which are commonly used in today’s SoC design flows. Most of the extraction programs use patternmatching methods which introduces an improvable error factor due to the pattern interpolation, and an intrinsically inescapable error factor from the difference of boundary conditions in the electro-magnetic field solver. Here, we study impact of the intrinsic error on timing and crosstalk noise estimation. We experimentally show that the resulting delay and noise estimation errors show a scatter which is normally distributed. Values of the standard deviations will help designers consider the intrinsic error com