Shuhei Iwade

A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications

In sub-100-nm generation, gate-tunneling leakage current increases and dominates the total standby leakage current of LSIs based on decreasing gate-oxide thickness. Showing that the gate leakage current is effectively reduced by lowering the gate voltage, we propose a local dc level control (LDLC) for SRAM cell arrays and an automatic gate leakage suppression driver (AGLSD) for peripheral circuits. We designed and fabricated a 32-kB 1-port SRAM using 90-nm CMOS technology. The six-transistor SRAM cell size is 1.25 /spl mu/m/sup 2/. Evaluation shows that the standby current of 32-kB SRAM is 1.2 /spl mu/A at 1.2 V and room temperature. It is reduced to 7.5% of conventional SRAM.

Reexamination of SRAM Cell Write Margin Definitions in View of Predicting the Distribution

Four definitions of static random access memory (SRAM) cell write margins (WMs) were reexamined by analyzing the dependence of the WM on the SRAM cell transistor threshold voltages (Vths) in order to find a preferable definition. The WM is expected to obey the normal distribution if the differential coefficients of the WM to Vths are constant over a wide range of Vth variations. This means that the write yield can be easily predicted by a small number of measured samples. Using SPICE in 45-nm technology, we examined which definition had Vth linearity, as well as giving an accurate write limit. The distribution predicted from the linearity was verified by the Monte Carlo simulation. As a result, the definition proposed by Gierczynski was found to be the most suitable definition for predicting the distribution and the write yield.

Test structure measuring inter- and intralayer coupling capacitance of interconnection with subfemtofarad resolution

We present a new test structure measuring inter- and intralayer coupling capacitance parasitic to the same target interconnection with subfemtofarad resolution. The coupling capacitance as well as fringing capacitance measured by the test structure are demonstrated for two-level copper interconnections used in 90-nm technology node. In addition, we demonstrate that the accuracy of layout parameters extraction is improved by nondestructive inverse modeling of a copper interconnect cross-sectional structure, which reproduces the pitch dependence of the measured inter- and intralayer coupling capacitance within about a 1% error.

Analysis of Pull-in Range Limit by Charge Pump Mismatch in a Linear Phase-Locked Loop

In this paper, we show the relationship between the pull-in range of a linear phase-locked loop (PLL) and the current mismatch of the charge pump that controls the frequency of the oscillator in the PLL. We evaluate the pull-in range of the PLL based on a nonlinear behavioral model of the pull-in process with three types of phase detectors. We introduce the mismatch error to the charge pump current in the PLL and study the impact of this error on the pull-in range. We also apply the mismatch error to a nonlinear differential equation that describes the loop dynamics of the PLL and calculate the pull-in range under this mismatch condition. We validate the limitations of the pull-in range due to the current mismatch by a numerical simulation with MATLAB.

The D30V/MPEG multimedia processor

MPEG-2 decoding and encoding are important applications for multimedia systems. Real-time capability and low-cost implementation are the main design considerations for these systems. Due to the high computational requirements of real-time applications, multimedia systems typically use special-purpose processors to handle data. However, due to the inherent inflexibility of their designs, these dedicated processors are of little use in various application environments-digital videocassette recorders, for example. This article introduces Mitsubishis D30V/MPEG multimedia processor, which integrates a dual-issue RISC with minimal hardware support for a real-time MPEG-2 decoder. This approach is advantageous because of the small chip area it requires and the flexibility of the easy-to-program RISC processor for multimedia applications.

Energy Efficient Stepwise Charging of a Capacitor Using a DC-DC Converter With Consecutive Changes of its Duty Ratio

Energy storage technology is becoming more and more important in todays environmentally conscious society. In the conventional method of directly charging a capacitor under a constant power supply voltage, the amount of energy dissipation is the same as the energy stored in the capacitor. In this paper, we propose the stepwise charging of a capacitor by consecutively changing the duty ratio of the DC-DC down converter. In N step charging, the energy dissipation is reduced to one Nth when compared with the conventional direct charging. The reduction of the dissipated energy is verified by SPICE simulations and by breadboard experiments, through which an energy reduction of one fourth and one eighth is confirmed from the measured power supply currents in four and eight step charging, respectively.

Simultaneous enlargement of SRAM read/write noise margin by controlling virtual ground lines

The SRAM operating margin in 65nm technology is analyzed. The peak characteristic in the read margin versus the supply voltage was found to be caused by the channel length modulation effect. Controlling the memory cell virtual ground line proved to be effective in enlarging the operating margin simultaneously in the read and the write operations. A simple optimum circuit which does not require any dynamic voltage control is proposed, realizing an improvement in the operating margin comparable to conventional circuits requiring dynamic voltage control.

Expansion of SRAM operation margin by adaptive voltage supply

This paper describes the expansion of the operation margin of the SRAM by optimizing the supply voltage condition. To find the optimum voltage, the whole SRAM circuit is designed, which includes the worst case memory cells for the read and the write operations considering the local Vth fluctuation. By the SPICE simulation using 45-nm parameters, successful operation is obtained for wide Vth range by controlling voltages of the word line, the power line and the GND line of memory cells. As a result, the stable operation was confirmed for the wide Vth range of 0.25V-0.65V. By using these results, we can rescue a lot of LSIs which fail under the normal voltage condition.

A study on fast motion estimation algorithm

This paper presents a new fast motion estimation algorithm. It searches groups of 4-pixels simultaneously and uses the value concatenated the absolute difference of upper 2-bit with the exclusive OR of the lower 6-bit. The search accuracy results show that the sum of absolute difference value is increased 4 of 7 video sequences when compared to the full-search algorithm with 4-bit absolute difference accumulator. The circuit was described in Verilog HDL and synthesized to Altera EP4CE30F23I7 FPGA. The synthesis results show that the required cycle is reduced by 61%, the circuit size is reduced by 15.2% and the operating frequency is increased from 334.67 MHz to 616.90 MHz when compared to the full-search algorithm with 4-bit absolute difference accumulator.

A study on motion estimation algorithm for moving pictures

In this paper, the operation cycle for Motion Vector Search is evaluated between the proposed search method and the conventional Full Search algorithm. As a result, the operation cycle of the proposed method is 74% smaller than Full Search algorithm but the circuit size is 0.8% larger than that of Full Search algorithm and the vector matching accuracy of the proposed search method deteriorate to 66.8%, when compared with Full Search algorithm.