Hisakazu Sato

The D30V/MPEG multimedia processor

MPEG-2 decoding and encoding are important applications for multimedia systems. Real-time capability and low-cost implementation are the main design considerations for these systems. Due to the high computational requirements of real-time applications, multimedia systems typically use special-purpose processors to handle data. However, due to the inherent inflexibility of their designs, these dedicated processors are of little use in various application environments-digital videocassette recorders, for example. This article introduces Mitsubishis D30V/MPEG multimedia processor, which integrates a dual-issue RISC with minimal hardware support for a real-time MPEG-2 decoder. This approach is advantageous because of the small chip area it requires and the flexibility of the easy-to-program RISC processor for multimedia applications.

A rule based logic reorganization system LORES/EX

The authors describe a rule-based logic reorganization system LORES/EX, which transforms an existing logic circuit into one that is dependent on other technology. The system can be not only flexibly adjustable to technology changes, but also has several special features as follows: (1) introduction of the circuit standardization rules makes the size of the rule base much smaller, and makes the description and modification of the rules easier; (2) application of conflict resolution based on evaluation functions contributes to the generation of high-quality circuits; and (3) introduction of the automatic partitioning of a circuit into subcircuits enables the reorganization of the circuit with some 10 K gates in a practical computation time.<<ETX>>

A 1.8 V 36 mW DSP for the half-rate speech codec

A low-power 16-bit DSP has been developed to realize a low bit-rate speech codec. A dual datapath architecture and low-power circuit design techniques are employed to reduce power consumption. The PDC half-rate speech codec is implemented in the DSP with 36 mW at 1.8 V.

A data-driven architecture for distributed parallel processing

A single-chip data-driven microprocessor with special functions for distributed parallel processing is described. The implemented functions necessary for parallel processing are: relative addressing mode for program memory; efficient test and set operation of arbitrary data in data memory; transparent access of distributed shared memory; and dynamic load distribution among multiprocessors. With this microprocessor, practical parallel processing systems which exploit a wide area of scientific applications can be constructed.<<ETX>>