Shuichi Samata

A new cell structure with a spread source/drain (SSD) MOSFET and a cylindrical capacitor for 64-Mb DRAM's

A new cell structure for realizing a small memory cell size has been developed for 64-Mb dynamic RAMs (DRAMs). The source/drain regions of a switching transistor are raised by using a selective silicon growth technique. Because of lateral growth of the silicon over gate and field regions, the bitline contact can overlap the gate and field regions. The shallow source/drain junction by the raised source/drain structure realizes a reduction of gate length and isolation spacing. As a result, the DRAM memory cell area can be reduced to 37% of that using the conventional LDD MOSFET. In the fabrication of an experimental DRAM cell, a new stacked capacitor structure has been introduced to maintain enough storage capacitance, even in the small-cell area. The new capacitor is made by a simple and unique process using a cylindrical silicon-nitride sidewall layer. It has been verified that this cell structure has the potential to realize multimegabit DRAMs, such as 64-Mb DRAMs. >

Improvement of thin oxide quality by hydrogen annealed wafer

Drastic improvement of a wafer quality has been carried out by high temperature anneal in hydrogen. A thin oxide formed on the hydrogen annealed wafer (HAI) has been found to have excellent behavior. In addition, electrical and physical evaluations verify that the HAI wafer does not have any disadvantage compared to the CZ wafer. The HAI wafer is promising for the substrate used in ULSI manufacture.<<ETX>>

Quarter-micron selective-epitaxial-silicon refilled trench (SRT) isolation technology with substrate shield

In order to realize high-density and stress-free field isolation for future ULSIs, the authors propose a selective-epitaxial-silicon refilled trench (SRT) isolation. The SRT isolation structure consists of a thin insulator film on the trench sidewalls, a selective-epitaxial-growth (SEG) silicon layer refilling the trench, and a capping oxide covering the trench openings. By using this isolation, the number of isolation process steps can be reduced to 60% of the number for a conventional process, and the stress induced by the thermal process can be minimal. The authors have succeeded in fabricating a 0.2- mu m isolation structure and have confirmed its excellent characteristics.<<ETX>>

Virtual fab technology utility simulation and its application to 300mm CR facility design and energy reduction

A new concept for facility design and electric power/energy analysis is introduced We developed the virtual fab simulator comprising of the lot flow simulator and the utility simulator called as FRS, fab resource simulator. With this simulator, we can estimate more accurate utility, and evaluate the reduction items. N2 facility size, for example, can be reduced by over 50% compared with the conventional method. The simulator also can be applied to analyzing the electric power consumptions of tools and reveals that the idle state power occupies approximately 1/3 of the total tool consumptions. Thus the virtual fab simulator is quite useful for efficient facility design and its analysis

Spread source/drain (SSD) MOSFET using selective silicon growth for 64 Mbit DRAMs

A novel MOSFET structure which has a small occupied area for 64-Mb DRAMs (dynamic RAMs) is proposed. The source-drain regions are raised by using a selective silicon growth technique. Because of lateral growth of the silicon over the gate and the field, the contact area can overlap the gate and the field. Moreover, the shallow source-drain junction of the raised source-drain structure realizes the reduction of the gate length and the isolation spacing. As a result, the MOSFET can minimize the total occupied area. It has been verified that this MOSFET has the potential to realize high-density LSIs such as 64-Mb DRAMs.<<ETX>>