Yukihiro Ushiku

Analysis of resistance behavior in Ti- and Ni-salicided polysilicon films

The sheet resistance of TiSi/sub 2/-polycide (TiSi/sub 2/-polysilicon) lines increases as they are made narrower. This phenomenon has been investigated in detail. It is found that the relationship between sheet resistance and line width (W) is characterized by three distinct regions according to the value of W. The abrupt increase in sheet resistance observed in the region W/spl les/0.2 /spl mu/m cannot be explained in terms of the phase transition from C54 to C49, which we show to be the cause of the rising resistance at larger W. By adopting a new test pattern for sheet resistance measurements and using it in combination with TEM and EDX analysis we conclude that the cause of this abrupt increase is the presence of large inter-grain layers where silicide is very sparse. On the contrary, NiSi films have no such inter-grain layers, and good resistance values can be obtained even with 0.1 /spl mu/m lines. The NiSi process appears to be a suitable candidate to replace TiSi/sub 2/ in future deep-sub-micron high-speed CMOS devices. >

Technology trends of silicon-on-insulator-its advantages and problems to be solved

Recent progress in SOI technology is reviewed and problems which need be solved are discussed. Emphasis is placed on the substrate floating effect, for which the bandgap engineering method is proposed for the first time. It is demonstrated that Si-Ge formation in the source region can improve the drain breakdown voltage significantly.<<ETX>>

Suppression of the floating-body effect in SOI MOSFET's by the bandgap engineering method using a Si/sub 1-x/Ge/sub x/ source structure

The bandgap engineering method using a SiGe source structure is presented as a means to suppress the floating-body effect in SOI MOSFETs. Experiments using Ge implantation are carried out to form a narrow-bandgapped SiGe layer in the source region. It has been confirmed that Ge-implanted SIMOX exhibited a 0.1 eV bandgap narrowing with a relatively low Ge-dosage of 10/sup 16/ cm/sup -2/. The fabricated N-type SOI-MOSFETs exhibited suppressed parasitic bipolar effects, such as improvement of the drain breakdown voltage or latch voltage, and suppression of abnormal subthreshold slope. Advantages over other conventional methods are also discussed, indicating that the bandgap engineering provides a practical method to suppress the floating-body effect.

P-MOSFET's with ultra-shallow solid-phase-diffused drain structure produced by diffusion from BSG gate-sidewall

A p-MOSFET structure with solid-phase diffused drain (SPDD) is proposed for future 0.1- mu m and sub-0.1- mu m devices. Highly doped ultrashallow p/sup +/ source and drain junctions have been obtained by solid-phase diffusion from a highly doped borosilicate glass (BSG) sidewall. The resulting shallow, high-concentration drain profile significantly improves short channel effects without increasing parasitic resistance. At the same time, an in situ highly-boron-doped LPCVD polysilicon gate is introduced to prevent the transconductance degradation which arises in ultrasmall p-MOSFETs with lower process temperature as a result of depletion formation in the p/sup +/-polysilicon gate. Excellent electrical characteristics and good hot-carrier reliability are achieved. >

Low-resistance ultrashallow extension formed by optimized flash lamp annealing

Flash lamp annealing (FLA) technology is proposed as a new method of activating implanted impurities. By optimizing FLA and implantation conditions, junction depth (Xj) at the concentration of 1 /spl times/ 10/sup 18/ cm/sup -3/ and the sheet resistance of 13 nm and 700 /spl Omega//sq for As and 14 nm and 770 /spl Omega//sq for BF/sub 2/ with junction leakage lower than 1 /spl times/ 10/sup -16/ A//spl mu/m/sup 2/ at 1.5 V were successfully obtained without wafer slip and warpage problems.

Agglomeration Resistant Self-Aligned Silicide Process Using N 2 Implantation into TiSi 2

An agglomeration resistant self-aligned silicide (SALICIDE) process using N2 implantation into TiSi2 films has been developed. The film morphology and the film sheet resistance after high-temperature annealing in an Ar ambient were evaluated as a function of implanted nitrogen doses. High implantation doses of 5×1016 cm-2 or more realized the completely flat film after the annealing; however there is an optimum dose of approximately 1×1016 cm-2 for maintaining the film sheet resistance at its minimum value. This phenomenon could be explained by the fact that the main composition of the film was changed from TiSi2 (C54) to TiN with a 5×1016 cm-2 or more nitrogen implantation and that the TiN film contains Si crystals. A successful application of this technique to a 0.8 µm n-MOS transistor is also presented.

Suppression of the floating-body effects in SOI MOSFETs by bandgap engineering

The floating-body effects, which are regarded as the most critical issues in applying Silicon-On-Insulator (SOI) devices to actual LSIs, can be suppressed by the reduction in bandgap energy in the source region. In addition to an increase in the drain breakdown voltage, the suppression of both kinks in I/sub d/-V/sub d/ characteristics and threshold voltage shift with an increase in drain voltage are achieved in sub-quarter micron Nch thin-film SOI MOSFETs.

A novel selective Ni/sub 3/Si contact plug technique for deep-submicron ULSIs

A contact filling-technique that utilizes polysilicon plug formation followed by Ni silicidation with a TiN barrier at the polysilicon plug bottom is described. Self-aligned complete silicidation of both shallow and deep contacts can be achieved at the same time by using the TiN silicidation stop. By using this technique in place of a polysilicon plug, low contact resistance was achieved for both n/sup +/ and p/sup +/ contacts. A completely silicided plug for both shallow and deep contact holes can be achieved at the same time. The low leakage current of junction diodes and lack of transistor characteristic degradation when using the Ni silicide plug demonstrate the integrity of the technique.<<ETX>>

Performance fluctuations of 0.10 /spl mu/m MOSFETs-limitation of 0.1 /spl mu/m ULSIs

The authors have recently demonstrated that 0.1 /spl mu/m gate length CMOS devices normally operate at room temperature. Moreover, they have experimentally shown that the threshold voltage of MOSFETs fluctuates due to the statistical fluctuations of channel dopant number, n/sub a/, which increases by reducing the gate length. Even if the individual 0.1 /spl mu/m MOSFETs operate normally, can one succeed in fabricating 0.1 /spl mu/m region ULSIs without failure ? To obtain the answer, it is necessary to study the performance fluctuations of 0.1 /spl mu/m region MOSFETs. This paper discusses the peculiar fluctuations of the threshold voltage and the transconductance of 0.10 /spl mu/m gate length NMOSFETs, using an 8 k MOSFET array and mentions their physical mechanism. Finally, the performance fluctuations of 0.1 /spl mu/m region ULSIs are estimated.<<ETX>>

Highly sensitive inspection system for lithography-related faults in agile-fab - detecting algorithm for monitoring and evaluation of yield impact

The authors performed automatic detection of lithography-related faults by characteristic factors calculated from fail bit count (FBC) data. They used the autocorrelation function to define a characteristic factor for a certain lithography-related failure mode. The frequency of lithography-related faults was monitored as time series data. Also, components of the characteristic factor quantified the direction of the inclination of lithography-related patterns. They changed according to time. The origin of faults varies with patterns. Thus, it is presumed that their causes differed with each period. Fault sourcing for a failure mode was carried out by correlating machine data and the characteristic factor with /spl chi//sup 2/ test. Since the characteristic factor included only one failure factor, this test could be performed with high sensitivity. The authors classified lithography-related faults and evaluated their yield impact from their frequency and yield loss automatically.