Shuji Hirao

Extremely Low Keff (1.9) Cu Interconnects with Air Gap Formed Using SiOC

Dual damascene Cu interconnects with Keff below 2.0 have been demonstrated for the first time. Air gaps between Cu lines were formed with a low K SiOC film in a carefully designed manner. CoWP cap layers were introduced to protect the Cu lines and to eliminate a dielectric liner layer. In addition, AGE (Air Gap Exclusion) was applied to solve crucial problems related to the air gaps. Keff of 1.9 was obtained at 65 nm design rule, which surpassed by far ITRS target (2.5~2.8) for hp 45. It was also confirmed that leakage current between lines was suppressed by the formation of the air gaps.

Plasma Damage of Gate Oxide through the Interlayer Dielectric

The degradation of thin gate oxides connected with the interconnect under the interlayer dielectric(IlD) by Ar plasma inadiation was observed. The electric field of gate oxide breakdown and the total charge to breakdovn(QBD were dependent on the material of the ILD. The current density through the ILD, calculated from QBD, was nearly equal to the measured value. Plasma damage through the ILD is caused mainly by the leakage current of the ILD. A-3-3

Highly manufacturable ELK integration technology with metal hard mask process for high performance 32nm-node interconnect and beyond

High performance 32nm-node interconnect with ELK (Extremely Low-k, k=3D2.4) has been demonstrated. To suppress process damage and enlarge the via-line space with a wide lithography process margin, robust ELK film with a metal hard mask (MHM) self-aligned via process has been developed. It has accomplished both ultimate low capacitance wirings and high TDDB reliability between Cu lines with vias. In addition, a novel technique of interface engineering between ELK and a liner layer has been developed to strengthen the tolerance against chip packaging. This has achieved highly reliable chip packaging. This complete process has a high manufacturability and it therefore offers a promising technology for the 32-nm node and beyond.

Effects of Ru-Ta Alloy Barrier on Cu Filling and Reliability for Cu Interconnects

A Ru-Ta alloy is applied to Cu dual damascene interconnects due to its good wettability with Cu. Using Ru-Ta alloy film as a barrier layer, filling property of ECP-Cu is improved and complete filling for trenches of 45 nm in width can be achieved. Although further optimization of CMP process is necessary, Ru-Ta alloy barrier also improves estimated lifetime of electromigration.

Effects of N doping in Ru-Ta alloy barrier on film property and reliability for Cu interconnects

RuTa(N) film has been prepared by doping N in Ru-Ta alloy and investigated its use as a barrier layer against Cu diffusion in Cu interconnects. It was found that RuTa(N) has a poor barrier property against Cu in the BEOL process, since N in Ru-Ta alloy is desorbed and RuTa(N) is recrystallized by heat treatment. It was also shown that RuTa(N) has inferior reliability due to its poor wettability with Cu compared to RuTa. On the other hand, RuTa has both good barrier property and superior reliability performance. It is possible to apply RuTa single film as a barrier layer for Cu interconnects.

A 0.9 µm pixel size image sensor realized by introducing organic photoconductive film into the BEOL process

A stacked image sensor with a 0.9 μm pixel size fabricated by using organic photoconductive film (OPF) was realized. It is the first trial to introduce an active material, that is, an organic semiconductor into the BEOL process. This pixel structure is fabricated by using a standard 45 nm BEOL process. However, after OPF deposition, it is essential to restrict the thermal budget and to avoid oxygen, moisture, and plasma irradiation. By controlling the above conditions, a demonstration of a stacked image sensor with OPF, which has high sensitivity, high saturation charge, and a wide incident light angle, was successfully performed.