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Featured researches published by Kousaku Yano.


The Japan Society of Applied Physics | 1993

Plasma Damage of Gate Oxide through the Interlayer Dielectric

Shuji Hirao; Tatsuo Sugiyama; Takehito Yoshida; Kousaku Yano; Noboru Nomura

The degradation of thin gate oxides connected with the interconnect under the interlayer dielectric(IlD) by Ar plasma inadiation was observed. The electric field of gate oxide breakdown and the total charge to breakdovn(QBD were dependent on the material of the ILD. The current density through the ILD, calculated from QBD, was nearly equal to the measured value. Plasma damage through the ILD is caused mainly by the leakage current of the ILD. A-3-3


Japanese Journal of Applied Physics | 1994

A Low Parasitic Capacitance Scheme by Thermally Stable Titanium Silicide Technology for High Speed Complementary-Metal-Oxide-Semiconductor

Takehito Yoshida; Shinichi Ogawa; Akio Miyajima; Kousaku Yano

This paper presents a dopant drive-out process from elevated source/drain (S/D) structures with titanium silicide local interconnects, which reduces not only the S/D areas but also junction capacitance in advanced complementary-metal-oxide-semiconductor (CMOS) fabrication. A low-oxygen-content process with an optimized boron (B) doping realizes a thermally stable titanium silicide with reduced Ti–B compound formation. Electrical measurements of the metal-oxide-semiconductor field effect transistors (MOSFETs) show good I-V characteristics and high endurance to short-channel effects. Furthermore, the MOSFETs have hot-carrier and bias-temperature aging properties similar to those of controlled devices. Consequently, it has been clarified that the delay time per stage of the MOSFETs with the local interconnects can be reduced with decreasing junction capacitance.


The Japan Society of Applied Physics | 1994

High Temperature Void Formation Induced by H2O in Al Interconnection with SiN/PSG Passivation

Tetsuya Ueda; Satoshi Ueda; Kousaku Yano; Noboru Nomura

l.Introduction One of the most important issues in VLSI metallization reliability is an open failure caused by the so-called stress-induced void formation of Al interconnection. It has been reported that slit-like or wedge-like voids in low temperature mode are due to thermal expansion coefficient mismatches between surrounding materials 1). However, the mechanism of round-shaped void formation of Al interconnection has not been well clarified, occu..ing during heating period at high temperature above 400oC when SiN/PSG passivation is used 2). When SOG is used as an interlevel dielectric, the outgasing of H2O from SOG films was considered to affect the round-shaped void formation 3). The purpose of this paper is to make clear the relation between HZO content in PSG and round-shaped void formation of Al interconnection covered with SiN/PSG passivation. The H2O behavior is studied by TEM, thermal desorption spectroscopy (TDS) and stress measurement.


The Japan Society of Applied Physics | 1993

A Low Parasitic Capacitance Scheme by Thermally Stable Titanium Silicide Technology for High Speed CMOS

Takehito Yoshida; Shinichi Ogawa; Akio Miyajima; Kousaku Yano

This paper presents titanium silicided junctions by a dopant drive-out process from elevated source/drain (S/D) structures combined with titanium silicide local interconnects, which reduce not only the S/D areas but also junction capacitance in advanced CMOS fabrication. The local interconnects which extend over field oxides are directly connected to the lining for the whole S/D regions. The titanium silicide of the local interconnects is formed from a reaction of an amorphous (a)-Si/Ti bilayer. A low oxygen content process with boron (B) doping using an optimized implantation energy realizes a thermally stable titanium silicide with reduced Ti-B compound formation. The delay time per stage of the MOSFETs with these local interconnects is about 18Vo faster than that of conventional contact structure devices.


The Japan Society of Applied Physics | 1992

The Suppression of Precipitation in Boro-Phospho-Silicate-Glass Films by Surface Control by Silylation (SCS) Process

Kousaku Yano; Yuka Terai; Sin-ichi Imai; Tetsuya Ueda; Satoshi Ueda; Masayuki Endoh; Noboru Nomura

Simple su rf ace control by silylation (SCS) process is developed for suppression of precipitation in high impurity concentrations BPSG films. Increase in impurity concentrations causes a precipitation problem by moisture penetration. This process employs exposure to the vaporized hexamethyldisilazane or that spin coating after BPSG films deposition. Silylation then occurs at the BPSG su rface. Silyl radicals change BPSG surface from a hydrophilic to a hydrophobic one.


Archive | 1999

Apparatus and method for forming thin film

Yuichiro Yamada; Naoki Suzuki; Ryuzo Houchin; Noboru Nomura; Kousaku Yano; Yuka Terai


Archive | 1996

Semiconductor device and associated fabrication method

Tatsuo Sugiyama; Shuji Hirao; Kousaku Yano; Noboru Nomura


Archive | 1989

Method for fabricating interconnection structure

Hiroshi Yamamoto; Tsutomu Fujita; Takao Kakiuchi; Kousaku Yano; Shuichi Tanimura; Shinji Fujii


Archive | 1997

Multi-layer wiring structure having varying-sized cutouts

Kousaku Yano; Tetsuya Ueda


Archive | 1993

Thin layer forming method wherein hydrophobic molecular layers preventing a BPSG layer from absorbing moisture

Kousaku Yano; Masayuki Endo; Yuka Terai; Noboru Nomura; Tomoyasu Murakami; Tetsuya Ueda; Satoshi Ueda

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