Shunji Kawaguchi

Design of a High Performance 2-GHz Direct-Conversion Front-End With a Single-Ended RF Input in 0.13

A 2.1 GHz CMOS front-end with a single-ended low-noise amplifier (LNA) and a double balanced, current-driven passive mixer is presented. The LNA drives an on-chip transformer load that performs single-ended to differential conversion. A detailed comparison in gain, noise, and second and third order linearity performance is presented to motivate the choice of a current-driven passive mixer over an active mixer. The front-end prototype was implemented on a 0.13 mum CMOS process and occupies an active chip area of 1.1 mm 2. It achieves 30 dB conversion gain, a low noise figure of 3.1 dB (integrated from 40 KHz to 1.92 MHz), an in-band IIP3 of -12 dBm, and IIP2 better than 39 dBm, while consuming only 12 mW from a 1.5 V power supply.

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A robust digitally assisted self-calibration technique is presented to improve the input-referred second-order-intermodulation intercept point (IIP2) of direct-conversion receivers. The low-power, low-noise 1.8-GHz CMOS receiver prototype relies on digital signal processing to improve analog/RF performance with only a minimum hardware overhead and with no performance penalties on the RF front end and analog baseband. The RF front end achieves an IIP2 better than 60 dBm without external filters between the LNA and downconversion mixers, has a conversion gain of 38.5 dB, a low DSB noise figure of 2.6 dB, and an IIP3 of -17.6 dBm. It consumes 15 mA from a 1.5-V supply, and occupies 1.56 mm2 on a 0.13-μm CMOS process.

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Direct conversion receivers offer a high level of integration for multiband applications. For standards operating in full duplex, like WCDMA, a very high IIP2 is needed due to transmit signal leakage. Several circuit, compensation and calibration techniques to improve the IIP2 have been developed, but they usually result in a trade-off between IIP2, area, power and other specifications [1,2]. The IIP2 is very sensitive to manufacturing variations and operating conditions such as supply voltage, LO power or frequency, and temperature. We present a robust automatic background self-calibration technique with minimal overhead and performance penalties on the receiver front-end or baseband due to its digital implementation (Fig. 3.8.1). Such digital IIP2 calibration is also free of mismatch. The 0.13µm 1.8GHz CMOS RF front-end without external filter between LNA and mixer has an IIP2 better than 60dBm-sufficient for WCDMA applications [3]- with a state-of-the-art noise figure and power consumption.

Digitally Assisted IIP2 Calibration for CMOS Direct-Conversion Receivers

Mobile WiMAX complying with the IEEE 802.16e standard is one of the emerging standards and is achieving world-wide penetration. Low-cost implementation is essential and single-chip implementation is a straightforward approach. However, there are many technical challenges such as floor-planning, signal integrity and scalability of analog/RF circuits in an SoC, as well as power reduction in scaled CMOS technologies. In this work, we have designed and fabricated a fully-integrated 2RX × 1TX dual-band direct-conversion transceiver having digital interfaces for a mWiMAX SoC in a 65nm pure CMOS technology. To cope with the constraints of floor-planning while maintaining the signal integrity, inductorless local oscillator (LO) distribution using compact dual-mode fractional dividers is introduced, leading to the reduction of die area. Total noise figure of 3.8dB is achieved by a novel noise-shaping transimpedance amplifier to mitigate the flicker noise of a scaled CMOS device.

A low-power low-noise direct-conversion front-end with digitally assisted IIP2 background self calibration

In this paper, a single-chip dual-mode 8-band 130 nm CMOS transceiver including A/D/A converters and digital filters with 312 MHz LVDS interface is presented. For a transmitter chain, linear direct quadrature modulation architecture is introduced for both W-CDMA/HSDPA (high speed uplink packet access) and for GSM/EDGE. Analog baseband LPFs and quadrature modulators are commonly used both for GSM and for EDGE. For a direct conversion receiver chain, ABB (analog base-band) blocks, i.e., LPFs and VGAs, delta-sigma A/D converters, and FIR filters are commonly used for W-CDMA/HSDPA (high speed downlink packet access) and GSM/EDGE to reduce chip area. Their characteristics can be reconfigured by register-based control sequence. The receiver chain also includes high-speed DC offset cancellers both in analog and in digital stage, and the self-contained AGC controller, whose parameters such as time constant are programmable to be free from DBB (digital base-band) control. The transceiver also includes wide-range VCOs and fractional PLLs, an LVDS driver and receiver for high-speed digital interface of 312 MHz. Measured results reveal that the transceiver satisfies 3GPP specifications for W-CDMA/HSPA (high speed packet access) and GSM/EDGE.

A fully integrated 2×1 dual-band direct-conversion transceiver with dual-mode fractional divider and noise-shaping TIA for mobile WiMAX SoC in 65nm CMOS

This paper describes a 2.1-GHz CMOS front-end with a single-ended low noise amplifier (LNA) and a double balanced, current-driven passive mixer. The LNA features an on-chip transformer load to perform single-ended to differential conversion. Implemented in a 0.13 um CMOS process, it achieves 30 dB conversion gain, a low noise figure of 3.1 dB, a 40 kHz 1/f noise corner, an in-band IIP3 of -12 dBm and IIP2 better than 39 dBm, while consuming only 12 mW from a 1.5 V power supply.

A single-chip 8-band CMOS transceiver for W-CDMA(HSPA) / GSM(GPRS) / EDGE with digital interface

A quadrature demodulator (QDEMOD) for WCDMA direct-conversion receiver using common-base input stage is reported. A common-base input stage is robust to parasitic elements and is suitable for on-chip matching circuits to realize small and low-cost RF front-end modules. However, a common-mode blocker signal, such as the transmitter (TX) leakage signal, degrades the noise performance due to intermodulation distortion of the TX leakage signal and noise. We propose a QDEMOD with a common-base input stage that is capable of suppressing the TX leakage signal using symmetrical inductors. The QDEMOD was fabricated using Si-Ge BiCMOS process with fT of 75 GHz. The measured results show that the NF degradation does not occur until the TX leakage signal input is larger than -13 dBm

A high performance 2-GHz direct-conversion front end with single-ended RF input in 0.13 um CMOS

A DC offset caused by self-mixing is a serious problem for direct-conversion receivers. Local oscillation (LO) leakage via quadrature demodulators (QDEMOD) must be suppressed in order to achieve a low DC offset. An LO buffer which drives QDEMOD mainly causes the LO leakage. We proposed an LO buffer which has a high-pass frequency response with small occupied area and low current consumption. A QDEMOD using the proposed LO buffer is fabricated using a SiGe BiCMOS process. Measured low LO leakage of -70dBm is achieved, which is 10 dB lower than that of a QDEMOD with a conventional LO buffer. This measured result indicates that the proposed LO buffer is suitable for QDE-MODs for direct-conversion receivers.

A Quadrature Demodulator for WCDMA Receiver Using Common-Base Input Stage with Robustness to Transmitter Leakage

A 900 MHz CMOS handy phone LSI is described. Three special RF-CMOS circuit technologies, fully integrated 900 MHz VCO with spiral inductor and varicap diode, new IF local frequency circuit, and effective image rejection system, are introduced.