Ryuichi Fujimoto

A 7-GHz 1.8-dB NF CMOS low-noise amplifier

A 7-GHz low noise amplifier (LNA) was designed and fabricated using 0.25µm-CMOS technology. A cascode configuration with a dual-gate MOSFET and shielded pads are adopted to improve the gain and the noise performances. The effects of the dual-gate MOSFET and the shielded pads are discussed quantitatively. The associated gain of 8.9dB, minimum noise figure of 1.8dB and input-referred 3rd-order intercept point of +8.4dBm were obtained at 7GHz. The LNA consumes 6.9mA from a 2.0V supply voltage. These measured results indicate the feasibility of a CMOS LNA with the appropriate techniques for low-noise and high-linearity applications over 5GHz.

0.15-/spl mu/m RF CMOS technology compatible with logic CMOS for low-voltage operation

Radio Frequency (RF) CMOS is expected to replace bipolar and GaAs MESFETs in RF front-end ICs for mobile telecommunications devices in the near future. In order for the RF CMOS to be popularly used in this application, compatibility of its process for high-speed logic CMOS and low supply voltage operation are important for low fabrication cost and low power consumption. In this paper, a 0.15-/spl mu/m RF CMOS technology compatible with logic CMOS for low-voltage operation is described. Because the fabrication process is the same as the high-speed logic CMOS, manufacturability of this technology is excellent. Some of the passive elements can be integrated without changing the process and others can be integrated with the addition of a few optional processes. Mixed RF and logic CMOS devices in a one-chip LSI can be realized with relatively low cost. Excellent high-frequency characteristics of small geometry silicon MOSFETs with low-power supply voltage are demonstrated. Cutoff frequency of 42 GHz of n-MOSFETs, which is almost the same level at that of general high-performance silicon bipolar transistors, was obtained. N-MOSFETs maintained enough high cutoff frequency of 32 GHz even at extremely low supply voltage of 0.5 V. Moreover, it was confirmed that degradation of minimum noise figure for deep submicron MOSFETs with 0.5 V operation is sufficiently small compared with 2.0 V operation. These excellent high-frequency characteristics of small geometry silicon MOSFETs under low-voltage operation are suitable for mobile telecommunications applications.

98 mW 10 Gbps Wireless Transceiver Chipset With D-Band CMOS Circuits

Recently, short-distance high-speed wireless communication using a 60 GHz band has been studied for mobile application. To realize higher-speed wireless communication while maintaining low power consumption for mobile application D band (110-170 GHz) is promising since it can potentially provide a wider frequency band. Thus, we have studied D-band CMOS circuits to realize low-power ultrahigh-speed wireless communication. In the D band, however, since no sufficient device model is provided, research generally has to start from device modeling. In this paper, a design procedure for D-band CMOS circuits is overviewed from the device layer to the system layer, where the architecture is optimized to realize both low power and high data transfer rate. Finally, a 10 Gbps wireless transceiver with a power consumption of 98 mW is demonstrated using the 135 GHz band.

A 60-GHz phase-locked loop with inductor-less prescaler in 90-nm CMOS

A 60-GHz phase-locked loop (PLL) with inductor-less prescaler is fabricated in a 90-nm CMOS process. The inductor-less prescaler has a smaller chip area than previously reported ones. The PLL operates from 61 to 63 GHz and consumes 78 mW from a 1.2 V supply. The phase noise at 100 kHz and 1 MHz offset from carrier are -72 and -80 dBc/Hz, respectively. The prescaler occupies 80 x 40 mum2. The active area of the PLL is 0.6 x 0.6 mm2.

A 60-GHz CMOS Receiver with Frequency Synthesizer

A 60-GHz receiver (RX) chip fabricated in 90 nm CMOS process is reported. The RX chip consists of an LNA, a downconversion mixer and a phase-locked loop synthesizer. The RX chip is capable of generating LO signal from phase-locked synthesizer. Measured power gain and NF of 22 dB and 8.4 dB were obtained at 61.5 GHz. These results indicate the possibility of realization of CMOS single-chip 60-GHz transceiver.

A 2.7-V, 200-kHz, 49-dBm, stopband-IIP3, low-noise, fully balanced gm-C filter IC

This 2.7 V low-distortion, low-noise, fourth order gm-C filter adopts real resistors for terminations and transconductors of wide common mode input range. Degradation in passband ripple due to mismatch between termination resistors and transconductors is alleviated by design centering. The filter achieves a stopband third-order intermodulation intercept point (IIP3) of 49 dBm, a passband IIP3 of 14 dBm, an input-referred noise of 28 nV//spl radic/(Hz) and a common mode rejection ratio of 70 dB. The cutoff frequency is tuned to 200 kHz using a reference resistor. The filter consumes 11.5 mA/channel. It operates even at 2.2 V with a stopband IIP3 of 40 dBm.

A 120-GHz transmitter and receiver chipset with 9-Gbps data rate using 65-nm CMOS technology

The design and measured results of a 120-GHz transmitter and receiver chipset are described in this paper. A simple amplitude shift keying (ASK) is adopted for this chipset. The proposed transmitter and receiver are fabricated using 65-nm CMOS technology. The current consumptions are 19.2 mA for the transmitter and 48.2 mA for the receiver. A 9-Gbps PRBS is successfully transferred from the transmitter to the receiver with the bit error rate less than 10−9.

A low local input 1.9 GHz Si-bipolar quadrature modulator with no adjustment

A 1.9 GHz quadrature modulator with an onchip 90/spl deg/ phase-shifter was fabricated using a silicon bipolar technology. This paper investigates error factors caused by a limiter amplifier. It is found that a gain enhancement technique in a phase-shifter circuit is effective in realizing an adjustment free quadrature modulator; we propose a new high-gain phase shifter circuit for this purpose. This technique employs a current mode interface and an on-chip inductor. An image-rejection ratio of over 45 dBc and a carrier feedthrough of below -40 dBc were attained at -15 dBm local oscillator power. This quadrature modulator operates at 2.7 V supply voltage. The operating frequency ranges from 1.2 GHz to 2.3 GHz. The die size of the quadrature modulator IC is 2.49 mm/spl times/2.14 mm.

135 GHz 98 mW 10 Gbps ASK transmitter and receiver chipset in 40 nm CMOS

An ASK transmitter and receiver chipset using 40 nm CMOS technology for wireless communication systems is described, in which a maximum data rate of 10 Gbps and power consumption of 98.4 mW are obtained with a carrier frequency of 135 GHz. A simple circuit and a modulation method to reduce power consumption are selected for the chipsets. To realize multi-gigabit wireless communication, the receiver is designed with consideration of the group delay optimization.

RF noise in 1.5 nm gate oxide MOSFETs and the evaluation of the NMOS LNA circuit integrated on a chip

Recently, direct tunneling gate oxide MOSFETs have shown the potential of enabling extremely high RF performance in analog applications. An excellent cutoff frequency of more than 150 GHz was reported at a gate length of less than 0.1 /spl mu/m. In this paper, RF noise characteristics of the MOSFETs are reported in detail. The gate oxide thickness and supply voltage dependencies were investigated. In addition, NMOS LNA (low noise amplifier) circuits made with 1.5 nm gate oxide MOSFETs were evaluated for the first time. Good RF analog circuit operation with very low noise and high gain was confirmed.