Yosuke Ogasawara

A −70dBm-sensitivity 522Mbps 0.19nJ/bit-TX 0.43nJ/bit-RX transceiver for TransferJet™ SoC in 65nm CMOS

TransferJet™ is an emerging high-speed close-proximity wireless communication standard, which enables a data transfer of up to 522Mbps within a few centimeters range. We have developed a fully integrated TransferJet SoC with a 4.48-GHz operating frequency and a 560-MHz bandwidth (BW) using 65nm CMOS technology. Baseband filtering techniques for both a transmitter (TX) and a receiver (RX) are proposed to obtain a sensitivity of -70dBm with low power consumption. The SoC achieves an energy per bit of 0.19nJ/bit and 0.43nJ/bit for the TX and the RX, respectively, We have also built the worlds smallest module prototype using the SoC, which is suitable for small mobile devices.

A fully integrated 2×1 dual-band direct-conversion transceiver with dual-mode fractional divider and noise-shaping TIA for mobile WiMAX SoC in 65nm CMOS

Mobile WiMAX complying with the IEEE 802.16e standard is one of the emerging standards and is achieving world-wide penetration. Low-cost implementation is essential and single-chip implementation is a straightforward approach. However, there are many technical challenges such as floor-planning, signal integrity and scalability of analog/RF circuits in an SoC, as well as power reduction in scaled CMOS technologies. In this work, we have designed and fabricated a fully-integrated 2RX × 1TX dual-band direct-conversion transceiver having digital interfaces for a mWiMAX SoC in a 65nm pure CMOS technology. To cope with the constraints of floor-planning while maintaining the signal integrity, inductorless local oscillator (LO) distribution using compact dual-mode fractional dividers is introduced, leading to the reduction of die area. Total noise figure of 3.8dB is achieved by a novel noise-shaping transimpedance amplifier to mitigate the flicker noise of a scaled CMOS device.

A single-chip 8-band CMOS transceiver for W-CDMA(HSPA) / GSM(GPRS) / EDGE with digital interface

In this paper, a single-chip dual-mode 8-band 130 nm CMOS transceiver including A/D/A converters and digital filters with 312 MHz LVDS interface is presented. For a transmitter chain, linear direct quadrature modulation architecture is introduced for both W-CDMA/HSDPA (high speed uplink packet access) and for GSM/EDGE. Analog baseband LPFs and quadrature modulators are commonly used both for GSM and for EDGE. For a direct conversion receiver chain, ABB (analog base-band) blocks, i.e., LPFs and VGAs, delta-sigma A/D converters, and FIR filters are commonly used for W-CDMA/HSDPA (high speed downlink packet access) and GSM/EDGE to reduce chip area. Their characteristics can be reconfigured by register-based control sequence. The receiver chain also includes high-speed DC offset cancellers both in analog and in digital stage, and the self-contained AGC controller, whose parameters such as time constant are programmable to be free from DBB (digital base-band) control. The transceiver also includes wide-range VCOs and fractional PLLs, an LVDS driver and receiver for high-speed digital interface of 312 MHz. Measured results reveal that the transceiver satisfies 3GPP specifications for W-CDMA/HSPA (high speed packet access) and GSM/EDGE.

A single-chip RF tuner / OFDM demodulator for mobile digital TV application

This paper presents the first published single-chip RF tuner / OFDM demodulator for a mobile digital TV application (1-segment broadcasting). To improve the minimum sensitivity, spurious signal suppression techniques are proposed. The single-chip RF tuner / OFDM demodulator using the proposed spurious signal suppression techniques is fabricated using 90nm CMOS technology and total die size is 3.26mm×3.26mm. By suppressing undesired spurious signals, the minimum sensitivity of −98.6dBm is achieved. The optimum current consumption is chosen for the RF tuner by using an adaptive control, the power consumption of the proposed single-chip receiver is only 60mW in medium-signal receiving mode.

A 3.2 mA-RX 3.5 mA-TX fully integrated SoC for Bluetooth Low Energy

A fully-integrated system-on-chip (SoC) for Bluetooth Low Energy (BLE) with 3.2 mA RX and 3.5 mA TX current consumption is presented. To achieve both low current consumption and high performance, the SoC employs a sliding-IF architecture that avoids out-of-band-blocking signals, a power management unit with improved efficiency, and techniques to reduce current in core circuits. The SoC achieves RX sensitivity of −93 dBm and maximum output power of 0 dBm. The SoC is in compliance with version 4.2 of the Bluetooth specifications and with the radio regulations of the FCC, ETSI, and ARIB. The SoC achieves the worlds lowest current consumption for both RX and TX modes in the published product-level SoCs.