Daisuke Miyashita

A phase noise minimization of CMOS VCOs over wide tuning range and large PVT variations

An automatic amplitude control circuit to minimize the phase noise of a LC-VCO is proposed and implemented by a 0.18-/spl mu/m CMOS process. The phase noise lower than -90dBc/Hz at 100kHz offset is achieved over a wide tuning range (from 2.2GHz to 2.8GHz) under large process (/spl Delta/V/sub th/ = /spl plusmn/100mV), temperature (from /spl sim/35/spl deg/C to 85/spl deg/C), and power supply (from 1.8V to 3V) variations.

An LDPC Decoder With Time-Domain Analog and Digital Mixed-Signal Processing

Time-domain analog and digital mixed-signal processing (TD-AMS) is presented. Analog computation is more energy- and area-efficient at the cost of its limited accuracy, whereas digital computation is more versatile and derives greater benefits from technology scaling. Besides, design automation tools for digital circuits are much more sophisticated than those for analog circuits. TD-AMS exploits both advantages, and is a solution better suited to implementing a system on chip including functions for which high computational accuracy is not required, such as error correction, image processing, and machine learning. As an example, a low-density parity-check (LDPC) code decoder with the technique is implemented in 65 nm CMOS and achieves the best reported efficiencies of 10.4 pJ/bit and 6.1 Gbps/mm2.

A 0.6V 380µW −14dBm LO-input 2.4GHz double-balanced current-reusing single-gate CMOS mixer with cyclic passive combiner

A mixer is one of the bottlenecks in achieving the low-voltage operation of a receiver. Most of the mixer topologies recently reported for low-voltage and low-power applications can be categorized into bulk-injection mixers or switching mixers. However, the bulk-injection mixer requires a large LO power with an accurate modeling of the back-gate effect [1]. Switching mixers also require a large LO power in the range of 0dBm for ideal switching operation [2–5]. In this work, a 0.6V mixer for Bluetooth specification with a target sensitivity of −90dBm [6], which requires a NF of 12dB and IIP3 of −7dBm, is described. None of the previously published designs [1–5] satisfies these specifications. A single-gate mixer [7], which was formerly used for mm-wave applications, is modified to fit the low-voltage and low-power 2.4GHz-band application.

A 10.4pJ/b (32, 8) LDPC decoder with time-domain analog and digital mixed-signal processing

Analog computation is potentially more efficient in certain arithmetic operations since a single wire can represent multiple bits of information, while digital systems retain advantages, for example, in logical operations. However, the use of conventional voltage-domain analog computation [1, 2] is limited due to its poor scalability, design complexity, and the overhead of interface circuits (i.e. ADC/DAC) to a surrounding digital system. Therefore, an alternate technique is required for exploiting the efficiency of analog computation. In this paper, we propose time-domain analog and digital mixed (TDMixed) signal processing, wherein time instead of voltage is utilized as the analog signal. To verify the validity of the TDMixed signal processing, we implement an (32, 8) low-density parity-check (LDPC) decoder in 65nm CMOS. The decoder achieves power and area efficiencies of 10.4pJ/b and 6.1Gb/s/mm2, respectively.

A −70dBm-sensitivity 522Mbps 0.19nJ/bit-TX 0.43nJ/bit-RX transceiver for TransferJet™ SoC in 65nm CMOS

TransferJet™ is an emerging high-speed close-proximity wireless communication standard, which enables a data transfer of up to 522Mbps within a few centimeters range. We have developed a fully integrated TransferJet SoC with a 4.48-GHz operating frequency and a 560-MHz bandwidth (BW) using 65nm CMOS technology. Baseband filtering techniques for both a transmitter (TX) and a receiver (RX) are proposed to obtain a sensitivity of -70dBm with low power consumption. The SoC achieves an energy per bit of 0.19nJ/bit and 0.43nJ/bit for the TX and the RX, respectively, We have also built the worlds smallest module prototype using the SoC, which is suitable for small mobile devices.

A fully integrated 2×1 dual-band direct-conversion transceiver with dual-mode fractional divider and noise-shaping TIA for mobile WiMAX SoC in 65nm CMOS

Mobile WiMAX complying with the IEEE 802.16e standard is one of the emerging standards and is achieving world-wide penetration. Low-cost implementation is essential and single-chip implementation is a straightforward approach. However, there are many technical challenges such as floor-planning, signal integrity and scalability of analog/RF circuits in an SoC, as well as power reduction in scaled CMOS technologies. In this work, we have designed and fabricated a fully-integrated 2RX × 1TX dual-band direct-conversion transceiver having digital interfaces for a mWiMAX SoC in a 65nm pure CMOS technology. To cope with the constraints of floor-planning while maintaining the signal integrity, inductorless local oscillator (LO) distribution using compact dual-mode fractional dividers is introduced, leading to the reduction of die area. Total noise figure of 3.8dB is achieved by a novel noise-shaping transimpedance amplifier to mitigate the flicker noise of a scaled CMOS device.

A low-IF CMOS single-chip Bluetooth EDR transmitter with digital I/Q mismatch trimming circuit

A single-chip low-IF transmitter for the Bluetooth enhanced data rate (max. 3Mbps) was fabricated in 0.18-/spl mu/m CMOS process. A quantitative study on the relation between the VCO pulling, intermediate frequency, and the linearity of the PA shows that the 1MHz-IF is the best solution. By a digital DC offset cancellation and I/Q mismatch trimming techniques, the LO and image signal leakages are suppressed below -40dBc and -50dBc, respectively.

Time-domain neural network: A 48.5 TSOp/s/W neuromorphic chip optimized for deep learning and CMOS technology

Demand for highly energy-efficient hardware for the inference computation of deep neural networks is increasing. Ultimately, fully spatially unrolled architecture where each distributed weight memory has a processing element (PE) for its exclusive use is the most energy-efficient solution because i) it can completely eliminate the energy-hungry data moving for weight fetching, and ii) PEs can consist only of combinational logics generally consuming less power than flip-flops. However, this strategy has not been applied because it requires a prohibitively huge amount of both area and hardware resources. We propose TDNN, which enables the fully spatially unrolled architecture by using 3D stacked ReRAM and the time-domain analog-digital mixed-signal processing that uses delay time as signal. In TDNN, a PE that performs synaptic operation is composed of only 12 logic transistors, which are equivalent to 3 gates. The proof-of-concept chip with SRAM instead of ReRAM shows unprecedentedly high energy efficiency of 48.2 TSop/s/W.

Low frequency spurs of VCO due to noise propagation from digital I/O's and their effects on performance of Bluetooth SoC

This paper describes the effect of digital noise on RF circuits on the single chip Bluetooth SoC. Low frequency components in the digital noise, generated by I/O circuits accessing to an external memory, are found to be converted to the phase noise as the spurs of voltage controlled oscillator (VCO). The spurs bring the performance degradation of wireless communications systems. To manage the gain of the VCO and the coupling coefficient is shown to be a key to mitigate the performance degradations.

A 1.2V 0.2-to-6.3GHz Transceiver with Less Than -29.5dB EVM@-3dBm and a Choke/Coil-Less Pre-Power Amplifier

1.2 V 0.2-to-6.3 GHz transceiver for a multimode radio is fabricated in a 0.13 mum CMOS technology is proposed. The transmitter achieves EVM of less than -29.5 dB at -3 dBm output from 0.2 to 7.2 GHz while consuming 69 mW, where the modulation scheme used is equivalent to 802.11a, 54Mb/s mode. Without any explicit matching components, S22 and S11 are kept less than -9.5 dB and -9.2 dB, respectively, over the frequency range from 0.1 to 6.3 GHz. To achieve wideband output matching, a parallel combination of a common-source amplifier and a source-follower buffer is used. This structure copes with both 50 Omega output resistance, and small output capacitance. The choke in the pre-power-amplifier (PPA) is also eliminated by adopting a push-pull amplifier and by using a modified envelope signal injection biasing scheme. The PPA achieves OP 1dB of 6 dBm, which corresponds to almost the rail-to- rail swing for 1.2 V power supply.