Kimio Ueda

Substrate-bias effect and source-drain breakdown characteristics in body-tied short-channel SOI MOSFET's

The substrate-bias effect and source-drain breakdown characteristics in body-tied short-channel silicon-on-insulator metal oxide semiconductor field effect transistors (SOI MOSFETs) were investigated. Here, substrate bias is the body bias in the SOI MOSFET itself. It was found that the transistor body becomes fully depleted and the transistor is released from the substrate-bias effect, when the body is reverse-biased. Moreover, it was found that the source-drain breakdown voltage for reverse-bias is as high as that for zero-bias. This phenomenon was analyzed using a three-dimensional (3-D) device simulation considering the body-tied SOI MOSFET structure in which the body potential is fixed from the side of the transistor. This analysis revealed that holes which are generated in the transistor are effectively pulled out to the body electrode, and the body potential for reverse-bias remains lower than that for zero-bias, and therefore, the source-drain breakdown characteristics does not deteriorate for reverse-bias. Further, the influence of this effect upon circuit operation was investigated. The body-tied configuration of SOI devices is very effective in exploiting merits of SOI and in suppressing the floating body-effect, and is revealed to be one of the most promising candidates for random logic circuits such as gate arrays and application specific integrated circuits.

Feasibility of 0.18 /spl mu/m SOI CMOS technology using hybrid trench isolation with high resistivity substrate for embedded RF/analog applications

A 0.18 /spl mu/m silicon on insulator (SOI) complementary metal-oxide semiconductor (CMOS) technology using hybrid trench isolation with high resistivity substrate is proposed and its feasibility for embedded RF/analog applications is demonstrated. The hybrid trench isolation is a combination of partial trench isolation and full trench isolation. In the partial trench isolation region, a part of the SOI layer remains under the field oxide so as to provide scalable body-tied SOI metal-oxide-semiconductor field-effect transistors (MOSFETs), while in the full trench isolation region, the whole of the SOI layer is replaced by the field oxide so as to provide high quality passives. It is demonstrated that this technology improves the maximum oscillation frequency and the minimum noise figure of the MOSFET and the Q-factor of the inductor, compared with bulk technology. Moreover, it is verified that the partial-trench-isolated body-tied structure suppresses the floating body effect of SOI devices for RF/analog applications and thus guarantees low-noise characteristics, stability, linearity, and reliability. It is concluded that this technology will be one of the key technologies for supporting the evolution of wireless communications.

A 128 kb SRAM with soft error immunity for 0.35 /spl mu/m SOI-CMOS embedded cell arrays

Summary form only given. Embedded cell arrays are more suitable for high-performance ASICs rather than gate arrays, because they can integrate high-quality building blocks such as high-density memories and optimized analog circuits together with digital logic circuits. This paper describes a 128 kb synchronous SRAM with body-fixed structure for embedded cell arrays using a 0.35 /spl mu/m SOI-CMOS process. The circuit performance and the soft error rate of the SRAM were measured and compared with those of a 128 kb SRAM with floating-body configuration.

Analysis of delay time instability according to the operating frequency in field shield isolated SOI circuits

It has been demonstrated that field shield (FS) isolation technology can suppress the delay time instability according to the operating frequency. The FS isolation technology has been proposed to fix the body potential without any area penalty in a gate array. In this technology, an FS plate, which is an additional polysilicon gate, is introduced to electrically isolate active regions. The body potential of the SOI MOSFET can be fixed through the SOI layer under the FS plate. The effect of body resistance on the delay time instability was also investigated using device simulation. The simulation showed that although the body potential momentarily falls to a nonsteady level due to capacitive coupling during switching operation, the body potential recovers to a steady level, following the RC law. From the simulation result, a helpful design guideline concerning the body resistance was deduced. This guideline showed that the FS isolation has a superior capability to suppress the frequency-dependent instability for practical deep submicron SOI circuits.

A 3.6-Gb/s 340-mW 16:1 pipe-lined multiplexer using 0.18 /spl mu/m SOI-CMOS technology

This paper describes a 16:1 multiplexer using 0.18 /spl mu/m SOI-CMOS technology. To realize ultra-high-speed operations, the multiplexer adapts a pipeline structure and a phase shift technique together with a selector architecture. This architecture takes advantage of the small junction capacitances of the SOI-CMOS devices. The multiplexer achieves 3.6 Gb/s at a supply voltage of 2.0 V, while dissipating only 30 mW at the core circuit and 340 mW for the whole chip which includes the I/O buffers.

3. Ogb/s, 272mw, 8:1 Multiplexer And 4.1gb/s, 388mw, 1:8 Demultiplexer

I . INTRODUCTION Optical transmission systems require multiplexer and demultiplexer chips as the major ingredients. There have been proposed and realized several architectures for multiplexers and demultiplexers. Such as the shift resister architecture, the interleaved architecture, the series gated architecture, and so on. In general, these previous architectures have aimed at high speed operation rather than low power dissipation. In multiplexers, the series gated architecture is effective in reducing power dissipation because the series gate can implement complex logic with fewer current sources. However, the architecture requires the 3-level for the series gate [l]. Thus it is difficult to lower the supply voltage for multiplexers. Furthermore, the architecture requires larger current to drive the 3-level series gate at high speed. On the other hand, the interleaved architecture is widely used in demultiplexers. In this architecture, conversion from serial to parallel data requires the lst, 2nd and 3rd stage flipflops [2]. This requires a large amount of hardware and therefore consumes much power. In this paper, 8:l multiplexer and 1% demultiplexer chips with low power dissipation are described. The multiplexer chip adopts the modified series gated architecture, while the demultiplexer chip adopts the modified interleaved architecture.

A sub 1-V SOI CMOS low noise amplifier for L-band applications

This paper describes a sub 1.0 V low noise amplifier in a 0.35 /spl mu/m SOI (silicon on insulator) CMOS process. Active-body control enables a sub 1.0 V operation, and improves gain and the 1 dB-compression point. The gain of 7.0 dB, the NF of 3.6 dB and the input 1 dB-compression point of -4.5 dBm are obtained at 1.0 V and 1.9 GHz.

High-Speed SOI 1/8 Frequency Divider Using Field-Shield Body-Fixed Structure

A high-speed silicon-on-insulator (SOI) 1/8 frequency divider with body-fixed structure was demonstrated using field-shield (FS) isolation. The maximum operation frequency is 2.1 GHz at 3.3 V. The SOI divider operates about 1.6 times faster than a bulk divider with the same dimensions. The normalized power consumption of the SOI divider at the maximum operating frequency is about 60% of that of the bulk divider. I d -V d transistor characteristics were improved, eliminating the kink in the saturation region, and the linearity of inverter characteristics was also improved with the body-fixed structure. The body contact collects excess carriers in the channel region, thereby preventing the parasitic bipolar action. From these results, it is suggested that devices using a field-shield body-fixed SOI structure have the potential for use in GHz-level systems containing analog circuits, and they are expected to be applied to portable communication systems and portable computers used in the multimedia era.

A 3.6 Gb/s 340 mW 16:1 pipe-lined multiplexer using SOI-CMOS technology

This paper describes a 16:1 multiplexer (MUX) using a 0.18 /spl mu/m partially-depleted SOI-CMOS technology. Owing to a selector type architecture with a pipeline structure as well as small junction capacitances of SOI-CMOS devices, the MUX achieves 3.6 Gbps operation dissipating 340 mW at a power supply of 2.0 V.

A 1.8 V 2.5 GHz PLL using 0.18 /spl mu/m SOI/CMOS technology

Summary form only given. This paper shows a 2.5 GHz PLL circuit for high-speed communication devices using a 0.18 /spl mu/m SOI/CMOS technology. The technology uses a shallow trench structure to effectively isolate active devices on a thin film SOI substrate. We employed floating-body SOI/CMOS in this chip. We applied a ring oscillator for the voltage controlled-oscillator (VCO). The well-known issues of SOI do not affect the circuit stability and noise performance of our PLL circuit for several reasons. Firstly, as the frequency range required for the VCO is comparatively narrow, the floating-body configuration would have little effect on circuit operation (Ueda et al., 1996). Secondly, thermal equilibrium on the ring oscillator can be achieved within a few microseconds (Tenbroek et al., 1998). Then the self-heating issue would be insignificant for the lock-in process of the PLL. Besides this, the buried oxide of SOI and shallow trench isolation reduces the crosstalk noise from the large digital logic block which is the most potentially serious problem for system-level integration of sensitive circuits and large logic blocks.