Shunli Ma

A 32.5-GS/s two-channel time-interleaved CMOS sampler with switched-source follower based track-and-hold amplifier

This paper presents a high speed and low distortion sampler with two-channel time-interleaved sampler with track-and-hold amplifier (THA). The THA is based on switched source-follower with active inductor load such that wide bandwidth in tack-mode and small signal feed-through in hold-mode can be both achieved within compact area. Furthermore, one clock-controlled auxiliary transistor is also introduced to cancel clock feed-through in hold-mode. The chip was fabricated in 65nm RF-CMOS process with core area of 0.07mm2 and power consumption of 192mW. The measured S-parameters show matched input and output up to 40GHz with 19.3GHz bandwidth in track-mode. The measured spurious-free-dynamic-range (SFDR) is 35dB, and total harmonic distortion (THD) is -30dB sampled at 16.26GS/s in one channel.

A 32.5-GS/s Sampler With Time-Interleaved Track-and-Hold Amplifier in 65-nm CMOS

This paper presents a high-speed and low feed-through sampler with two-channel time-interleaved track-and-hold amplifiers (THAs). The THA is based on switched buffer with active inductors load such that wide bandwidth in track-mode and small-signal feed-through in hold-mode can be both achieved within compact area. Furthermore, one clock-controlled auxiliary transistor is also introduced to cancel clock feed-through in hold-mode. With two-channel accurate on-chip clock and its distribution network, double sampling rate is achieved due to the two-channel time-interleaved structure used. The chip was fabricated in 65-nm RF-CMOS process with core area of 0.07 mm 2 and power consumption of 211 mW. The measurements show that the S-parameters matched input and output up to 40 GHz with 19.3-GHz bandwidth in track-mode, the spurious-free-dynamic-range above 35 dB and total harmonic distortion below -30 dB up to 6 GHz when the sampling rate is 16.26 GS/s for one channel.

A 75.7GHz to 102GHz rotary-traveling-wave VCO by tunable composite right /left hand T-line

With the use of tunable composite-right/left-hand (CRLH) transmission line (T-line), this paper provides a wide frequency-tuning-range (FTR) mechanism for Mobius-ring rotary-traveling-wave (RTW) VCO in millimeter-wave region. CRLH T-line is implemented in RTW-VCO with inductor-loaded transformer to realize sub-band selection over a wide FTR. Each sub-band is further covered by a varactor for fine-tuning. The chip was fabricated in GF 65nm RF-CMOS process with area of 0.08mm2. The measured results show a current consumption of 14mA under supply voltage of 1V, a tuning range of 29.5% with center frequency at 89.3GHz, and a phase noise from -100.08dBc/Hz to -98.7dBc/Hz with 10MHz offset. A state-of-art figure-of-merit FOMT of -177.78dBc/Hz is demonstrated.

An overview of new design techniques for high performance CMOS millimeter-wave circuits

CMOS millimeter-wave integrated circuits are more attractive due to its potential in higher integration with digital signal processing blocks and lower cost, compared to SiGe and GaAs. Meanwhile, the cut-off (ft) frequency of MOSFETs is continuously increased along with the scaling down of transistors as predicted with Moores law. However, CMOS process suffers from high substrate loss and low quality (Q) of passive devices. As a result, circuit performance is hindered with degraded main block such as VCO, divider and LNA. In this paper, some new structures, such as meta-material oscillator, tunable inductors and coupled oscillator, are summarized and demonstrated to overcome these problems in designing high performance millmeter-wave circuits in nano-CMOS.

A 131.5GHz, −84dBm sensitivity super-regenerative receiver by zero-phase-shifter coupled oscillator network in 65nm CMOS

A CMOS high-sensitivity super-regenerative receiver is proposed for millimeter-wave imaging systems. With quench-control signals, two LC-tank oscillators are coupled in-phase by zero-phase-shifter network in a positive feedback loop. This leads to a high oscillatory amplification and improves the detection sensitivity. The circuit is realized in 65nm CMOS with a core area of 0.06 mm2. Measurements show that the receiver features a sensitivity of -84dBm, a noise-equivalent-power of 0.615fW/Hz0.5, a noise-figure of 7.26 dB and a power consumption of 8.1mW.

A low-Power PGA with DC-Offset Cancellation in 65 nm CMOS process

A low-Power Programming Gain Amplifier (PGA) with DC-Offset Cancellation for long term evolution (LTE) is implemented in a 65-nm CMOS. The proposed PGA is composed of a three-stage sub-VGA with DC-offset cancellations (DCOC) and common-mode feedbacks (CMFB). The gain of the proposed PGA ranges from 0 dB to 42 dB with a step of 3 dB, which can be easily tuned by switched-resistors and switched-capacities. The proposed VGA achieves a tunable gain up to up to 6 dB by the first stage, up to 12 dB by the second stage, and up to 24 dB by the third stage respectively. The DCOC is adapted to cancel the DC offset voltage introduced by the mismatch presented in circuits. At the same time, CMFB is utilized to reduce the mismatch between the top and bottom current sources. It has a low power consumption of 2.76 mW at a supply of 1.2 V with 10 MHzs gain bandwidth (GBW), input-referred noise of 18 nV/vHz.

A 9.8 Gbps, 6.5 mW forwarded-clock receiver with phase interpolator and equalized current sampler in 65 nm CMOS

A full-rate energy-efficient forwarded-clock (FC) receiver is demonstrated in this paper. A current sampler with continuous-time equalization is realized with 20 GHz bandwidth in sampling for data recovery. Moreover, a phase interpolator is introduced to generate sampling clock with deskew for data recovery. The testing chip was fabricated in 65 nm CMOS process in area of 0.16 mm2. Measurement shows that the FC receiver can achieve a data-rate up to 9.8 Gbps and power consumption is 6.5 mW.

A 39 GHz–80 GHz millimeter-wave frequency doubler with low power consumption in 65nm CMOS tehnology

A wideband injection locking frequency doubler is proposed for millimeter wave frequency generation in CMOS. The circuit consists of two push-push pairs along with a cross-coupled oscillator which share a current source. The injection locking frequency doubler can generate frequencies from 39 GHz to 80.6 GHz, achieving a wide injection locking range of 69.5 %. The conversion gain of the doubler is more than -15dB in the whole locking range when driving a 30 fF capacitor. Designed in TSMC 65nm CMOS, the circuit has an active area of 340 × 180 um2. The injection locking frequency doubler consumes 11.8 mW dc power from 1.2V supply, while the output buffer consumes 5.96 mW.

A quadrature clock generator with calibration for 22∼31.4 GS/s real-time sampling system

This paper presents an accurate quadrature clock signals with phase calibration for ultra-high speed real-time sampling system. The proposed four-phase clock generator is a phase locked loop (PLL) with a novel quadrature divider which can realize tunable quadrature phase to calibrate variable mismatches. The operating frequency of the proposed quadrature clock can be tuned from 5.5GHz to 7.85GHz which can be used in four-channel time-interleaved sampler. The real-time sampling system achieve 28-31.2GS/s sampling rate. The chip consumes 28mW power with 1.2V supply voltage in TSMC 65 nm CMOS process. The measurements show that the calibration phase can cover ±10°I phase and Q phase mismatch. The phase noise is -115 dBc/Hz@1MHz offset frequency at 6.85GHz center frequency and cycle-to-cycle time RMS jitter is 210fs.