Chixiao Chen

A High-Linearity Pipelined ADC With Opamp Split-Sharing in a Combined Front-End of S/H and MDAC1

This paper presents a power-efficient, high-linearity pipelined ADC, utilizing a combined front-end of the sample/hold circuit (S/H) and the first multiplying digital-to-analog converter (MDAC1). In contrast with the conventional merged sample-and-hold amplifier (SHA) and first MDAC, the front-end uses an opamp split-sharing scheme to meet the different gain and bandwidth requirements of both the S/H and the first MDAC. This opamp split-sharing scheme mitigates the memory effect without a dedicated clock phase and avoids crosstalk. In the back-end ADC, 4.5-bit opamp-sharing MDACs with four-input operational trans-conductance amplifiers (OTAs) are used for further power saving. Implemented in a 0.18-μm CMOS process, the 14-bit ADC achieves a spurious-free dynamic range (SFDR) of 89.1 dB and a signal-to-noise plus distortion ratio (SNDR) of 70.2 dB, with a sampling rate of 100 MS/s and an input of 15.5 MHz. For input signals up to 220 MHz, measured SFDR and SNDR are maintained above 82.7 dB and 66.2 dB, respectively. The ADC consumes 92 mW with a 1.8-V supply, occupying an area of 6.3 mm2.

A 14-bit 200-MS/s time-interleaved ADC with sample-time error detection and cancelation

A 14-bit 200-MS/s time-interleaved analog-to-digital converter (TI-ADC) is presented. An adaptively-controlled sampling switch is proposed to correct the sample-time error between two interleaved channels and an auto-correlation-based sample-time error detection algorithm is introduced to detect the sample-time error. A prototype ADC is fabricated in a 0.18-μm mixed-signal CMOS process with a power consumption of 460 mW from a 1.8-V supply. The ADC achieves an SNDR of 68.5 dB and an SFDR of 88.5 dB for a 15.33MHz input.

A low-offset calibration-free comparator with a mismatch-suppressed dynamic preamplifier

This paper presents a new low offset comparator with a mismatch-suppressed dynamic preamplifier Various mismatches contribute to comparatorss input referred offset. The proposed mismatch suppression is achieved by sampling the mismatches at the dynamic preamplifiers output node during the precharge phase. A time-domain analysis method is utilized to quantize the suppression effects. By the techniques, a 1-GS/s four-input comparator is implemented by 65-nm CMOS technology. It achieves a 60-μW power dissipation and a 1.89-mV 1-sigma(σ) offset voltage, which is a 90% improvement compared to its non-suppressed counterparts.

Beyond-one-cycle loop delay CT ΔΣ modulators with proper rational NTF synthesis and time-interleaved quantizers

Currently, less-than-one-cycle loop delay is the key factor to impede higher clock rate and wide bandwidth continuous-time oversampling modulators. In this paper, a new method to develop a beyond-one-cycle delay CTDSM based on the proper rational NTF synthesis is proposed without an extra fast path . Also, further loop delay extending will be implemented by a fully s-domain deviation. Compared with the traditional impulse invariant way in DT-CT mapping, this new method shows a much simpler work. In the end, the paper discusses time-interleaved implementations in the proposed beyond-one-cycle delay modulators, including offset, gain and sampling time error mismatches between channels.

A digitally calibrated current-steering DAC with current-splitting array

The current-splitting architecture for the current-steering DAC can reduce the area of the current source array greatly. A background calibration technique for current-steering digital-to-analog (DAC) with the current-splitting array is presented. The proposed calibration technique can eliminate mismatch errors for both the upper bits array and the lower bits array in the background. A 14-bit current-steering DAC is fabricated in a 0.18μm CMOS process. The SFDR can be improved more than 20dB. The DAC achieves more than 80dB SFDR at 2MHz for a 200MS/s sampling rate. The active area is 1.26mm2 and power consumption is 125mW.

A 14-bit 200-MS/s time-interleaved ADC calibrated with LMS-FIR and interpolation filter

A digital background calibration for time-interleaved ADC is presented. By using LMS-FIR and interpolation filter, mismatches of offset, gain, bandwidth, and sample-time error are calibrated. Adaptively controlled by correlation evaluation, the calibration is applicable for most input cases. A 14-bit 200-MS/s two-channel time-interleaved ADC is prototyped in a 0.18-µm CMOS process with core area of 15.2 mm2. The ADC achieves an SFDR of 88.9 dBc and an SNDR of 69.5 dBc after calibration, consuming 460 mW at 1.8 V.

A 6-b 600 MS/s SAR ADC with a new switching procedure of 2-b/stage and self-locking comparators

This paper presents a 6-b successive approximation register (SAR) ADC at the sampling rate of 600 MHz in a 65 nm CMOS process. To pursue high speed, this design employs the idea of the 2-b/stage. Based on this, the proposed structure with a new switching procedure is presented. Compared with traditional structures, it optimizes problems cause by mismatches of DACs and saves power. In addition, this paper takes advantage of distributed comparator topology to improve the speed, while the proposed structure and self-locking technique lighten the kickback and offset caused by multiple comparators. The measurement results demonstrate that the signal-to-noise plus distortion ratio (SNDR) is 32.13 dB and the spurious-free dynamic range (SFDR) is 44.05 dB at 600 MS/s with 5.6 MHz input. By contrast, the SNDR/SFDR respectively drops to 28.46/39.20 dB with Nyquist input. Fabricated in a TSMC 65 nm process, the SAR ADC core occupies an area of 0.045 mm 2 and consumes power of 5.01 mW on a supply voltage of 1.2 V resulting in a figure of merit of 252 fJ/conversion-step.

A 500-1000MS/s 12-bit resolution level-shift bootstrapped switch

This paper presents a new high speed and high precision level-shift bootstrapped switch. By adopting analog source follower as a level shifter, instead of the traditional digital switches under the 65nm process, the full scale built-up time is reduced to 51.3ps which is much less than the latter. The simulation result shows that when the sampling frequency is 500MHz, the proposed bootstrapped switch achieves an ENOB of 12.56bit, an SNDR of 77.37dB, an SFDR of 78.02dB with a load of 2.5-pF sampling capacitor. The power consumption is 2.71 mW under 1.2V and 2.5V supply. While the sample frequency is 1GHz, the switch achieves an ENOB of 11.16bit, an SNDR of 68.33dB, an SFDR of 68.77dB with the same load. The power consumption under 1GHz sampling frequency is 2.87 mW under those supply.

A mixed sample-time error calibration technique in time-interleaved ADCs

Sample-time error between channels degrades resolution of time-interleaved analog-to-digital converters (TIADCs). A calibration method implemented in mixed circuits with low-complexity and fast-convergence is proposed in this paper. The algorithm for detecting sample-time error, which is widely applied to wide-sense stationary input signals, is based on correlation. The detected sample-time error is corrected by a voltage-controlled sampling switch. Experimental result of a 2-channel 200-MS/s 14-bit TIADC shows that the signal-to-noise-and-distortion ratio improves 19.1 dB, and the spurious-free dynamic range improves 34.6 dB for a 70.12MHz input after calibration. The convergence time of the calibration is about 20000 sampling intervals.

A sample-time error calibration technique in time-interleaved ADCs with correlation-based detection and voltage-controlled compensation

Sample-time error between channels degrades the resolution of time-interleaved analog-to-digital converters (TIADCs). A calibration method implemented in mixed circuits with low-complexity and fast-convergence is proposed in this paper. The algorithm for detecting sample-time error is based on correlation and widely applied to wide-sense stationary input signals. The detected sample-time error is corrected by a voltage-controlled sampling switch. Experimental result of the 2-channel 200-MS/s 14-bit TIADC shows that the signal-to-noise-and-distortion ratio improves 19.1 dB, and the spurious-free dynamic range improves 34.6 dB for a 70.12-MHz input after calibration. The convergence time of calibration is about 20000 sampling intervals.