Junyan Ren

A 1.1-Gb/s 115-pJ/bit Configurable MIMO Detector Using 0.13-

This brief presents an efficient and configurable multiple-input-multiple-output (MIMO) signal detector design solution and its high-speed IC implementation. This detector can support 2 × 2/3 × 3/4 × 4 MIMO and quadratic phase-shift keying/16-state quadratic amplitude modulation (QAM)/64-state QAM modulation configurations. The detection algorithm employs an early-pruned technique that can reduce up to 46% node extensions in the K-Best sphere decoder while maintaining an almost maximum-likelihood performance. A parallel multistage folded very large scale integration architecture is accordingly developed that can achieve high detection throughput and configurability. To further improve the IC implementation efficiency, this detector also uses a candidate-sharing structure for partial Euclidean distance calculation and a two-stage sorter for survivor node selection. A test chip has been fabricated using 0.13- m single-poly- and eight-metal (1P8M) CMOS technology with a core area of 3.9 mm2. Operating at 1.2-V supply with 137.5-MHz clock, the chip achieves 1.1-Gb/s throughput and consumes 115 pJ per bit, representing 40% more energy efficient than state of the art in the open literature.

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To provide wide frequency tuning range (FTR) with compact implementation area, a new inductive tuning method is introduced in this paper for CMOS 60 GHz voltage controlled oscillator (VCO). The inductive tuning is based on a switching inductor-loaded transformer by configuring different current return-paths in the secondary coil of the transformer. Different from previous inductive tuning methods, the proposed VCO topology can achieve wide FTR for multiple sub-bands at 60 GHz within compact area by only one transformer. Two 60 GHz VCOs are demonstrated in 65 nm CMOS with design targets for the maximum FTR and the balanced phase noise in each sub-band, respectively. As measured by experiments, the first VCO (asymmetric) achieves a wide FTR of 25.8% from 51.9 to 67.3 GHz with phase noise variation of ±8.2 dB ( -90.2 to -106.7 dBc/Hz at 10 MHz offset) in all sub-bands; and the second VCO (symmetric) realizes a low phase noise variation of ±2.5 dB ( -105.9 to -110.8 dBc/Hz at 10 MHz offset) in all sub-bands with a FTR of 14.2% from 57.0 GHz to 65.5 GHz.

CMOS Technology

This paper presents a low-voltage and low-distortion CMOS bootstrapped switch that adopts a new technique to improve the accuracy of sample-and-hold (S/H) circuits. In order to reduce distortion due to variation of the gate overdrive and the threshold voltage in conventional bootstrapped switches, a PMOS-type bootstrapped circuit combining with a NMOS-type one forms a double sampling switch that transmits input signals to the output terminal. The switch reduces the on-resistance greatly and keeps it constant, resulting in precise sampling of signals and better input bandwidth. A test S/H circuit based on this switch was designed and fabricated in SMIC 0.18-mum CMOS mixed signal technology. Experiments show at 100 MSample/s, a peak signal-to-noise-and-distortion ratio (SNDR) of 100.9 dB, spurious-free dynamic range (SFDR) of 102 dB and total harmonic distortion (THD) of 101 dB can be acquired, and for input frequency up to the Nyquist frequency, this circuit maintains SNDR over 90 dB, SFDR and THD better than 92.7 dB, respectively

Design and Analysis of Wide Frequency-Tuning-Range CMOS 60 GHz VCO by Switching Inductor Loaded Transformer

A 2.1-GHz dividerless PLL with low power, low reference spur and low in-band phase noise is introduced in this paper. A new phase detection mechanism using aperture-phase detector (APD) and phase-to-analog converter (PAC) generates an analog voltage in proportion to the phase error between reference and VCO, and then controls the current amplitude of the following charge pump (CP). The charging and discharging currents in the proposed CP have equal pulse width and equal small amplitude in locked state, which reduces the reference spur and power consumption of the CP effectively. Moreover, compared to the conventional CP with the same bias current in locked state, the proposed CP can contribute a much lower noise to the PLL output. In addition, a method of tunable loop gain with theoretical analysis is introduced to reduce the PLL output jitter. The proposed PLL is fabricated in a standard 0.13-μm CMOS process. It consumes 2.5 mA from a 1.2-V supply voltage and occupies a core area of 0.48 mm × 0.86 mm. The reference spur of the proposed PLL is measured to be -80 dBc/-74 dBc and an in-band phase noise of -103 dBc/Hz at 100 kHz offset is achieved.

A High-Speed High-Resolution Low-Distortion CMOS Bootstrapped Switch

This paper presents a dual-mode voltage-controlled oscillator (DMVCO) and a DMVCO-based wideband frequency synthesizer for software-defined radio applications. The DMVCO allows the synthesizer to leverage single-sideband (SSB) mixing, a power efficient approach, for high-frequency local oscillator (LO) signal generation, without the need of poly-phase filter or quadrature voltage-controlled oscillator (QVCO). When compared to the QVCO approach, the DMVCO solution allows the synthesizer to provide continuous LO signals without frequency gaps. The synthesizer is implemented in a 0.13-μm CMOS technology, occupying an active area of 2.2 mm2 and consuming 34-77 mW of power. It provides in-phase and quadrature-phase LO signals over the frequency bands of 0.4-3- and 5-6 GHz and differential LO signals from 0.4 to 6 GHz, supporting major wireless standards including DVB-T, GSM, WCDMA, TD-SCDMA, WLAN802.11 a/b/g, and Bluetooth. The measured phase noises are -135 and -124 dBc/Hz at 3-MHz offset under 1.8- and 5.15-GHz carriers, respectively. The measured spurious tones are less than - 42 dBc at the SSB mixer output.

A Dividerless PLL With Low Power and Low Reference Spur by Aperture-Phase Detector and Phase-to-Analog Converter

A 14-bit 100-MS/s pipelined ADC in 0.18 µm 1P6M CMOS process is presented. A new sampling technique is introduced which achieves high linearity over wide bandwidth by eliminating the major sources of distortion at low and high input frequencies. The ADC uses digital background calibration, featuring a shuffled-dithering scheme, to obtain a DNL of +0.18/−0.18 LSB and an INL of +1.1/−0.6 LSB. It achieves over 85dB SFDR and 65dB SNDR within the first Nyquist zone, maintains over 74 dB SFDR and 63 dB SNDR for input signals up to 400 MHz and consumes 220 mW at 1.8 V supply.

A 0.4–6-GHz Frequency Synthesizer Using Dual-Mode VCO for Software-Defined Radio

A new 8PBF structure for 64/128 flexible point FFT processor is proposed. The processor, which is based on 8*8*2 mixed radix algorithm, can deal with multiple inputs more efficiently for MIMO applications. The 8PFB structure efficiently brings the throughput of the processor up to 1GS/s and the chances of register reverse down, reducing the power dissipation remarkably. Meanwhile the modified shift-add algorithm can remove complex multipliers in the FFT processor.

A digitally calibrated 14-bit linear 100-MS/s pipelined ADC with wideband sampling frontend

This paper has explored an ultra-low-power design of two 60-GHz direct-conversion receivers in a 65-nm CMOS process for single-channel and multi-channel applications under the IEEE 802.15.3c standard, respectively. One subthreshold biasing 0.4-V transconductance mixer is designed with a compact quadrature hybrid coupler (160 μm × 210 μm with measured 3-dB intrinsic loss) in receivers to achieve low power (8 mW for single channel and 12.4 mW for multi-channel) and high gain (55 dB for single channel and 62-dB for multi-channel). One three-stage low-noise amplifier employs high- Q passive matchings. A double-layer-stacked inductor is utilized for matching in the single-channel receiver and a high-impedance transmission line is utilized for matching in the multi-channel receiver, respectively. In addition, one new modified Cherry-Hooper amplifier is applied for the variable-gain amplifier design to achieve high gain-bandwidth product and high power efficiency. The single-channel receiver is implemented with 0.34- mm2 chip area. It is measured with a power consumption of 8 mW, a minimum single-sideband noise figure (NF) of 4.9 dB, a 3-dB bandwidth of 3.5 GHz, and a maximum conversion gain of 55 dB. The multi-channel receiver is implemented with 0.56- mm2 chip area. It is measured with a power consumption of 12.4 mW, a 3-dB bandwidth of 8 GHz (59.5 ~ 67.5 GHz), and a maximum conversion gain of 62 dB. The measurement results show that the two demonstrated 60-GHz direct-conversion receivers can achieve high gain and low NF with ultra-low power in 65-nm CMOS.

Design of Low-Power, 1GS/s Throughput FFT Processor for MIMO-OFDM UWB Communication System

Performance failure has become a significant threat to the reliability and robustness of analog circuits. In this article, we first develop an efficient non-Monte-Carlo (NMC) transient mismatch analysis, where transient response is represented by stochastic orthogonal polynomial (SOP) expansion under PVT variations and probabilistic distribution of transient response is solved. We further define performance yield and derive stochastic sensitivity for yield within the framework of SOP, and finally develop a gradient-based multiobjective optimization to improve yield while satisfying other performance constraints. Extensive experiments show that compared to Monte Carlo-based yield estimation, our NMC method achieves up to 700X speedup and maintains 98% accuracy. Furthermore, multiobjective optimization not only improves yield by up to 95.3% with performance constraints, it also provides better efficiency than other existing methods.

Design of Ultra-Low-Power 60-GHz Direct-Conversion Receivers in 65-nm CMOS

This paper presents a power-efficient, high-linearity pipelined ADC, utilizing a combined front-end of the sample/hold circuit (S/H) and the first multiplying digital-to-analog converter (MDAC1). In contrast with the conventional merged sample-and-hold amplifier (SHA) and first MDAC, the front-end uses an opamp split-sharing scheme to meet the different gain and bandwidth requirements of both the S/H and the first MDAC. This opamp split-sharing scheme mitigates the memory effect without a dedicated clock phase and avoids crosstalk. In the back-end ADC, 4.5-bit opamp-sharing MDACs with four-input operational trans-conductance amplifiers (OTAs) are used for further power saving. Implemented in a 0.18-μm CMOS process, the 14-bit ADC achieves a spurious-free dynamic range (SFDR) of 89.1 dB and a signal-to-noise plus distortion ratio (SNDR) of 70.2 dB, with a sampling rate of 100 MS/s and an input of 15.5 MHz. For input signals up to 220 MHz, measured SFDR and SNDR are maintained above 82.7 dB and 66.2 dB, respectively. The ADC consumes 92 mW with a 1.8-V supply, occupying an area of 6.3 mm2.