Sujiang Rong

Analysis and Design of Transformer-Based Dual-Band VCO for Software-Defined Radios

This work presents complete analysis of both one- port and two-port dual-band oscillators using transformer-based fourth-order LC tanks, from which critical parameters including oscillation frequency, start-up condition, tank Q, phase noise-are thoroughly derived and compared. It is shown that one-port oscillators consume less power than two-port counterparts but may suffer from stability problem which can be solved by a notch-peak cancellation technique. On the other hand, compared to one-port oscillators, two-port oscillators need to consume more power to obtain the same output swing, but their phase noise can be improved more linearly with increasing bias current, and thus they can achieve lower phase noise with a sufficiently large bias current. Based on the results, a dual-band quadrature voltage- controlled oscillator (Q-VCO) is systematically designed and implemented in a 0.13- m CMOS process for software-defined -radio (SDR) applications, in which the two-port topology is used in the low band for low phase noise and the one-port topology is employed in the high band for low power consumption. The prototype achieves a dual-band operation with in-phase and quadrature-phase (IQ) output signals from 2.7 GHz to 4.3 GHz and from 8.4 GHz to 12.4 GHz. At 3.6 GHz and 10.4 GHz, phase noise at 3 MHz offset of dBc/Hz and dBc/Hz and sideband-rejection ratios (SBR) of 37 dB and 41 dB are measured, respectively.

A Single-Chip UHF RFID Reader in 0.18

A single-chip UHF RFID reader that integrates all building blocks-including an RF transceiver, IQ data converters, and a digital baseband-is implemented in a 0.18 mum CMOS process. A high-linearity RX front-end and a low-phase-noise synthesizer are proposed to handle the large self-interferer, which is a key challenge in the reader RX design. Highly reconfigurable mixed-signal baseband architecture for channel-selection filtering is proposed to achieve power optimization for multi-protocol operation with different system dynamic ranges and data rates. The reader dissipates a maximum power of 276.4 mW when transmitting maximum output power of 10.4 dBm and receiving the tags response of -70 dBm in the presence of -5 dBm self-interferer while occupying 18.3 mm2.

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An interpolative-phase-tuning (IPT) technique is proposed to tune the frequency of millimeter-wave (MMW) LC-based ring oscillators without using varactor. As a key feature, the tradeoff between tank Q and tuning range of the proposed IPT oscillators is independent of the operation frequency, which makes the IPT technique suitable for applications at MMW frequencies. Moreover, the IPT oscillators can achieve larger frequency tuning range and much better phase accuracy over the tuning range as compared to the conventional gm-coupled LC oscillators for multiphase generation. Two IPT oscillator prototypes are designed and implemented in a 0.13-μm CMOS process. The first one operates at 50 GHz with eight output phases and measures phase noise of -103.7 dBc/Hz at 1-MHz offset and -127.8 dBc/Hz at 10-MHz offset, tuning range of 6.8%, and figure of merit (FOM) of 186.4 dB while occupying chip area of 0.36 mm2. The second prototype oscillates at 60 GHz with four output phases and measures phase noise of -95.5 dBc/Hz at 1-MHz offset, -120.6 dBc/Hz at 10-MHz offset, tuning range of 9%, and FOM of 180.6 dB with chip area of 0.2 mm2.

CMOS Process

Frequency dividers are key components for frequency synthesis in wireless and wireline communication systems. Among different types of frequency dividers, LC-based injection-locked frequency dividers (ILFDs) feature high-frequency operation at low power consumption, but their locking range is quite narrow due to the high-Q nature of the resonator. Recently, design techniques to enhance the locking range of ILFDs have been reported. Injection into two coupled LC oscillators [1] and sandwiched injection into two identical LC oscillators [2] are proposed, but these techniques are suitable for dividers with quadrature outputs. Inductive-peaking and transconductance enhancement techniques [3, 5] are also used but they require extra inductors and thus larger chip area. In this paper, a simple but effective technique is presented to improve the locking range of ILFDs without extra inductive components while consuming low power.

Design and Analysis of Varactor-Less Interpolative-Phase-Tuning Millimeter-Wave LC Oscillators with Multiphase Outputs

A transformer-feedback injection-locked divide-by-3 frequency divider (ILFD) is proposed. Employing a transformer feedback, the divider can achieve high performance in terms of low voltage, high frequency, and low power consumption. Fabricated in a 0.13-mum CMOS process and operated at a 1-V supply voltage, the divider prototype measures an input frequency range from 22.7 GHz to 25.1 GHz with 2nd and 3rd harmonic tones of -45 dBc and -40 dBc respectively. With quadrature outputs, the divider achieves a sideband rejection ratio of 40 dB while consuming 1.7 mW and occupying an active area of 0.23 mm2.

0.9mW 7GHz and 1.6mW 60GHz frequency dividers with locking-range enhancement in 0.13µm CMOS

A notch-peak cancellation concept is introduced in transformer-based LC tanks to achieve a dual-band quadrature VCO. Fabricated in 0.18 μm CMOS process and operated at 1V supply, the QVCO prototype measures a stable dual-band operation from 3.27 GHz to 5.02 GHz and from 9.48 GHz to 11.36 GHz. At 4.2 GHz and 10 GHz, the QVCO measures phase noise at 1 MHz offset of -116.3 dBc/Hz and -112 dBc/Hz, and sideband rejection ratios (SBR) of 49 dB and 47 dB while drawing 6 mA and 10 mA, respectively. The QVCO occupies an active area of 0.88 mm2.

A 1V 1.7mW 25GHz transformer-feedback divide-by-3 frequency divider with quadrature outputs

An 860MHz-960 MHz UHF RFID reader is designed in 0.18- μm CMOS that fully integrates an RF transceiver and a digital baseband. Highly reconfigurable mixed-signal baseband architecture for channel-selection filtering is proposed to achieve optimal power consumption for multi-protocol operation with different system dynamic ranges and data rates. In the talk mode with LNA bypassed, the RX measures a sensitivity of 70 dBm in the presence of a 5 dBm self-interferer. In the listen mode, LNA is turned on, and RX sensitivity is 90 dBm is measured. The TX achieves output power from -9 to lldBm with output P-ldB of 10.4 dBm.

A 1V 4 GHz-and-10 GHz transformer-based dual-band quadrature VCO in 0.18 μm CMOS

This brief presents a fully integrated frequency synthesizer for software-defined radios covering not only all the existing wireless standards from 47 MHz to 10 GHz [including 14-band multiband orthogonal frequency-division modulation (MB-OFDM) ultrawideband (UWB)] but also the gigabits per second wireless communication around 60 GHz. A dual-band quadrature output voltage-controlled oscillatior reconfigurable as either a one-port oscillator for low power consumption or a two-port oscillator for low phase noise is employed as the core to generate all the frequencies from 47 MHz to 6 GHz. A multimode x3/x5/x7 injection-locked frequency multiplier and a single-sideband mixer with a tunable transformer-based narrow-band load are proposed to generate the carrier frequencies for the 14 MB-OFDM and impulse UWB bands with fast settling time, low power, and small chip area. An automatic amplitude calibration (APC) technique is proposed to greatly increase the locking range of the subharmonic injection-locked oscillators with achieving a given output amplitude. Implemented in a 0.13-μm CMOS process, the synthesizer prototype occupies an active area of 3 μm2, consumes 33-83 mW in total, and measures phase noise of -139.6 dBc/Hz at 3-MHz offset from a 1.7-GHz carrier.

Single-Chip UHF RFID reader in 0.18- μm CMOS

Extensive research has been focused on generating LO signals for software-defined radios (SDRs) with ultra-wide tuning range over several frequency decades and sufficiently high spectrum purity to support diverse wireless standards [1–5]. This work presents an integrated frequency synthesizer (FS) that is able to cover not only all the wireless standards from 47MHz to 10GHz including 14-band MB-OFDM UWB but also the 802.15.3c standard from 57 to 66GHz.

A 0.05- to 10-GHz, 19- to 22-GHz, and 38- to 44-GHz Frequency Synthesizer for Software-Defined Radios in 0.13-

An interpolative-phase-tuning technique is presented to tune the frequency of millimeter-wave LC-based ring oscillators without using varactors. Two oscillator prototypes are designed and implemented in a 0.13-µm CMOS process. The first oscillator operates at 50GHz with 8 output phases and measures phase noise of −127.8dBc/Hz at 10MHz offset, tuning range of 6.8%, and figure of merit (FOM) of 186.4dB while occupying chip area of 0.36mm2. The second prototype oscillates at 60GHz with 4 output phases and measures phase noise of −120.6dBc/Hz at 10MHz offset, tuning range of 9%, and FOM of 180.6dB with chip area of 0.2mm2.