Shy-Jay Lin

A 90-nm CMOS device technology with high-speed, general-purpose, and low-leakage transistors for system on chip applications

A leading edge 90nm bulk CMOS device technology is described in this paper. In this technology, multi Vt and multi gate oxide devices are offered to support low standby power (LP), general-purpose (G or ASIC), and high-speed (HS) system on chip (SoC) applications. High voltage I/O devices are supported using 70/spl Aring/, 50/spl Aring/, and 28/spl Aring/ gate oxide for 3.3V, 2.5V, and 1.5-1.8V interfaces, respectively. The backend architecture is based on nine levels of Cu interconnect with hot black diamond (HBD) low-k dielectric (k<=3.0).

Reflective electron-beam lithography: progress toward high-throughput production capability

Maskless electron beam lithography can potentially extend semiconductor manufacturing to the 16 nm technology node and beyond. KLA-Tencor is developing Reflective Electron Beam Lithography (REBL) targeting high-volume 16 nm half pitch (HP) production. This paper reviews progress in the development of the REBL system towards its goal of 100 wph throughput for High Volume Manufacturing (HVM) at the 2X and 1X nm nodes. We will demonstrate the ability to print TSMC test patterns with the integrated system in photoresist on silicon wafers at 45 nm resolution. Additionally, we present simulation and experimental results that demonstrate that the system meets performance targets for a typical foundry product mix. Previously, KLA-Tencor reported on the development of a REBL tool for maskless lithography at and below the 16 nm HP technology node1. Since that time, the REBL team and its partners (TSMC, IMEC) have made good progress towards developing the REBL system and Digital Pattern Generator (DPG) for direct write lithography. Traditionally, e-beam direct write lithography has been too slow for most lithography applications. E-beam direct write lithography has been used for mask writing rather than wafer processing since the maximum blur requirements limit column beam current - which drives e-beam throughput. To print small features and a fine pitch with an e-beam tool requires a sacrifice in processing time unless one significantly increases the total number of beams on a single writing tool. Because of the continued uncertainty with regards to the optical lithography roadmap beyond the 16 nm HP technology node, the semiconductor equipment industry is in the process of designing and testing e-beam lithography tools with the potential for HVM.

Reflective electron beam lithography: lithography results using CMOS controlled digital pattern generator chip

Maskless electron beam lithography can potentially extend semiconductor manufacturing to the 10 nm logic (16 nm half pitch) technology node and beyond. KLA-Tencor is developing Reflective Electron Beam Lithography (REBL) technology targeting high-volume 10 nm logic node performance. REBL uses a novel multi-column wafer writing system combined with an advanced stage architecture to enable the throughput and resolution required for a NGL system. Using a CMOS Digital Pattern Generator (DPG) chip with over one million microlenses, the system is capable of maskless printing of arbitrary patterns with pixel redundancy and pixel-by-pixel grayscaling at the wafer. Electrons are generated in a flood beam via a thermionic cathode at 50-100 keV and decelerated to illuminate the DPG chip. The DPG-modulated electron beam is then reaccelerated and demagnified 80-100x onto the wafer to be printed. Previously, KLA-Tencor reported on the development progress of the REBL tool for maskless lithography at and below the 10 nm logic technology node. Since that time, the REBL team has made good progress towards developing the REBL system and DPG for direct write lithography. REBL has been successful in manufacturing a CMOS controlled DPG chip with a stable charge drain coating and with all segments functioning. This DPG chip consists of an array of over one million electrostatic lenslets that can be switched on or off via CMOS voltages to pattern the flood electron beam. Testing has proven the validity of the design with regards to lenslet performance, contrast, lifetime, and pattern scrolling. This chip has been used in the REBL demonstration platform system for lithography on a moving stage in both PMMA and chemically amplified resist. Direct imaging of the aerial image has also been performed by magnifying the pattern at the wafer plane via a mag stack onto a YAG imaging screen. This paper will discuss the chip design improvements and new charge drain coating that have resulted in a functional DPG chip and will evaluate the current chip performance on the REBL system. Print results for line/space and device test patterns at the 100nm node will be presented.

The REBL DPG: recent innovations and remaining challenges

Reflective electron-beam lithography (REBL) employs a novel device to impress pattern information on an electron beam. This device, the digital pattern generator (DPG), is an array of small electron reflectors, in which the reflectance of each mirror is controlled by underlying CMOS circuitry. When illuminated by a beam of low-energy electrons, the DPG is effectively a programmable electron-luminous image source. By switching the mirror drive circuits appropriately, the DPG can ‘scroll’ the image of an integrated circuit pattern across its surface; and the moving electron image, suitably demagnified, can be used to expose the resist-coated surface of a wafer or mask. This concept was first realized in a device suitable for 45 nm lithography demonstrations. A next-generation device has been designed and is presently nearing completion. The new version includes several advances intended to make it more suitable for application in commercial lithography systems. We will discuss the innovations and compromises in the design of this next-generation device. For application in commercially-practical maskless lithography at upcoming device nodes, still more advances will be needed. Some of the directions in which this technology can be extended will be described.

An instruction-based high-throughput lossless decompression algorithm for e-beam direct-write system

About 13-Terabyte data for Massive e-beam direct-write lithography (MEBDW) system, a potential solution for highvolume manufacturing (HVM) of 10-nm and beyond technology nodes in a 26 mm x 33 mm field of layout, is required. Therefore cost reduction on data storage and transmission through development of high compression rate of lossless data and high throughput real time decompression algorithms is necessary. In this paper, an instruction-based hybrid method (IBHM) is proposed. It is an asymmetric scheme to hybrid simple compression methods. The decompression is achieved by instruction-based decoding. The input layout image is partitioned into different fragments, compressed and encoded into instructions. On the MEBDW system side, the encoded bit-stream is decoded by the IBHM decoder. The function of this decoder is to execute only a minimal number of simple instructions, thus the decoder can be implemented with low gate-count on ASIC. Simulation results show that a single IBHM decoder is capable of providing an output data rate as high as ~50 Gbps in various masking layers.

Data path development for multiple electron beam maskless lithography

Electron beam lithography has been used in the production of integrated circuits for decades. However, due to the limitation of throughput it was not a viable solution for high volume manufacturing and its biggest application is the production of semiconductor masks. For many considerations it has particularly now become desirable to eliminate the semiconductor mask and introduce maskless lithography for semiconductor fabrication. Multiple Electron Beam Maskless Lithography (MEBML2) has been proposed as a solution to overcome the traditional source current limitation of an electron beam system by using many thousands of parallel electron beamlets to write a pattern directly on the wafer. In developing the MEBML2 tool the challenges have shifted and, in absence of the mask, the system data path has emerged as one of the central challenges. The main theme in the data path development is bandwidth. The required raw bandwidth at the patterning beams is determined by throughput and resolution, i.e. pixel size and number of intensity modulation levels. To achieve a production worthy throughput at 10 wafers per hour in a Gaussian-beam-based maskless lithography system, by writing 3.5-nm pixels at 2 levels (on/off) which is required for the 22-nm lithography node, the required aggregate bandwidth at the beam blanker array is up to 45 Tbit/s. Such a large bandwidth requirement means that the data path architecture is mainly characterized by the bandwidth of the data streams in the system. Compression techniques can be used to reduce the intermediate data stream bandwidth requirements and consequently lead to simplifying the system design, reducing power consumption and footprint, but come at the cost of increased data processing complexity and possible limitations on throughput. In this paper we will show results from the development of a prototype data path for the Gaussian-beam-based maskless lithography system. A new concept for data processing and storage is proposed. The vertex-based processing and storage technique is adopted to reduce memory usage considerably, with only modest requirements on the hardware resources. It reveals that a realistically implementable data path system for the maskless lithography tool in high volume manufacturing is feasible.

REBL DPG lenslet structure: design for charging prevention

KLA-Tencor is currently developing Reflective Electron Beam Lithography (REBL), targeted as a production worthy multiple electron beam tool for next generation high volume lithography. The Digital Pattern Generator (DPG) integrated with CMOS and MEMS lenslets is a critical part of REBL. Previously, KLA-Tencor reported on progress towards a REBL tool for maskless lithography below the 10 nm technology node. However, the MEMS lenslet structure suffered from charging up during writing, requiring the usage of a charge drain coating. Since then, the TSMC multiple e-beam team and the KLA-Tencor REBL team have worked together to further develop the DPG for direct write lithography. In this paper, we introduce a hollow-structure MEMS lenslet array that inherently prevents charging during writing, and preliminary verification results are also presented.

Influence of data volume and EPC on process window in massively parallel e-beam direct write

Multiple e-beam direct write lithography (MEBDW), using >10,000 e-beams writing in parallel, proposed by MAPPER, KLA-Tencor, and IMS is a potential solution for 20-nm half-pitch and beyond. The raster scan in MEBDW makes bitmap its data format. Data handling becomes indispensable since bitmap needs a huge data volume due to the fine pixel size to keep the CD accuracy after e-beam proximity correction (EPC). In fact, in 10,000-beam MEBDW, for a 10 WPH tool of 1-nm pixel size and 1-bit gray level, the aggregated data transmission rate would be up to 1963 Tera bits per second (bps), requiring 19,630 fibers transmitting 10 Gbps in each fiber. The data rate per beam would be <20 Gbps. Hence data reduction using bigger pixel size, fewer grey levels to achieve sub-nm EPC accuracy, and data truncation have been extensively studied. In this paper, process window assessment through Exposure-Defocus (E-D) Forest to quantitatively characterize the data truncation before and after EPC is reported. REBL electron optics, electron scattering in resist, and resist acid diffusion are considered, to construct the E-D Forest and to analyze the imaging performance of the most representative layers and patterns, such as critical line/space and hole layers with minimum pitch, cutting layers, and implant layers, for the 10-nm, and 7-nm nodes.

Contour-based kernel modeling and verification for E-Beam lithography

In E-beam lithography, the double or multiple Gaussian kernels used to describe the electron scattering behavior have been discussed extensively for critical dimensions (CDs) larger than the e-beam blur size. However in e-beam direct write on wafer, CD dimensions are close to the beam blur size because of requirements in both resolution and throughput. This situation gives rise to a severe iso-dense CD bias. Hence the accuracy of the modeling kernel is required to achieve a larger common process window. In this paper we present contour-based kernel modeling and verification for e-beam lithography. The edge contours of CD-SEM images of the contact hole array pattern with duty ratio splits are used in this Gaussian kernel modeling study. A 2-step optimization sequence is proposed to improve the fitting efficiency and robustness. In the first step, roundness is the primary and the most effective index at the corner region which is sensitive to determine the beam blur size. The next step is to minimize the deviation of the through-pitch proximity effect by adjusting the ratio of the electron backscattering to the electron forward scattering. The more accurate cost index, edge placement error, is applied in the subsequent optimization step with constrained beam blur sizes extracted from the previous step. The optimum modeling kernel parameters can be obtained by the lowest cost deviation of the simulation contours and the CD-SEM extracted edge contours after optimization iterations. For early study of the proximity impact on future EBDW systems, the exposure experiment is performed on an EBM-8000 mask writer to build the modeling kernel. The prediction accuracy of the optimum modeling kernel on 60-nm features with different pattern densities is also verified experimentally to be within 1.5 nm.

A study of conductive material for e-beam lithography

Unlike optical systems, electron-charging effect is a concern for e-beam lithography. Accumulated charge on the resist will perturb the route of incident electrons, resulting in pattern distortion or failure. Therefore, reducing charge accumulation becomes an important topic for high-pattern-density e-beam applications. In this paper, we used a conductive material as the resist substrate for charging effect evaluation. The e-beam source from CD-SEM (Critical Dimension SEM) was initially used to conductive performance qualification. When comparing with non-conductive BARC, we found that the experimental conductive material has an additional 11% to 14% resist-shrinkage than a non-conducting BARC. However, we cannot repeat this phenomenon in the multiple-e-beam (MEB) imaging tool. From Monte Carlo simulation, the electrons deeply penetrate through the substrate instead of being trapped in the resist substrate. It further indicates that although conductive bottom layer can dissipate electron effectively for surface charging, the film scheme as well as tool grounding are also important for minimizing the charging effect.